Unverified Commit 8f0450c5 authored by Paweł Anikiel's avatar Paweł Anikiel Committed by Arnd Bergmann
Browse files

dts: socfpga: Add Mercury+ AA1 devicetree 



Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA.

Signed-off-by: default avatarPaweł Anikiel <pan@semihalf.com>
Signed-off-by: default avatarJoanna Brozek <jbrozek@antmicro.com>
Signed-off-by: default avatarMariusz Glebocki <mglebocki@antmicro.com>
Signed-off-by: default avatarTomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: default avatarMaciej Mikunda <mmikunda@antmicro.com>
Reviewed-by: default avatarArnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20211021151736.2096926-2-pan@semihalf.com

'
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 5cbd8430

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -1091,6 +1091,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ 
	s5pv210-torbreck.dtb

dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \

	socfpga_arria5_socdk.dtb \

	socfpga_arria10_mercury_aa1.dtb \

	socfpga_arria10_socdk_nand.dtb \

	socfpga_arria10_socdk_qspi.dtb \

	socfpga_arria10_socdk_sdmmc.dtb \

arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts

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+112 −0
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// SPDX-License-Identifier: GPL-2.0

/dts-v1/;



#include "socfpga_arria10.dtsi"



/ {



	model = "Enclustra Mercury AA1";

	compatible = "altr,socfpga-arria10", "altr,socfpga";



	aliases {

		ethernet0 = &gmac0;

		serial1 = &uart1;

		i2c0 = &i2c0;

		i2c1 = &i2c1;

	};



	memory@0 {

		name = "memory";

		device_type = "memory";

		reg = <0x0 0x80000000>; /* 2GB */

	};



	chosen {

		stdout-path = "serial1:115200n8";

	};

};



&eccmgr {

	sdmmca-ecc@ff8c2c00 {

		compatible = "altr,socfpga-sdmmc-ecc";

		reg = <0xff8c2c00 0x400>;

		altr,ecc-parent = <&mmc>;

		interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,

			     <47 IRQ_TYPE_LEVEL_HIGH>,

			     <16 IRQ_TYPE_LEVEL_HIGH>,

			     <48 IRQ_TYPE_LEVEL_HIGH>;

	};

};



&gmac0 {

	phy-mode = "rgmii";

	phy-addr = <0xffffffff>; /* probe for phy addr */



	max-frame-size = <3800>;

	status = "okay";



	phy-handle = <&phy3>;



	mdio {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "snps,dwmac-mdio";

		phy3: ethernet-phy@3 {

			txd0-skew-ps = <0>; /* -420ps */

			txd1-skew-ps = <0>; /* -420ps */

			txd2-skew-ps = <0>; /* -420ps */

			txd3-skew-ps = <0>; /* -420ps */

			rxd0-skew-ps = <420>; /* 0ps */

			rxd1-skew-ps = <420>; /* 0ps */

			rxd2-skew-ps = <420>; /* 0ps */

			rxd3-skew-ps = <420>; /* 0ps */

			txen-skew-ps = <0>; /* -420ps */

			txc-skew-ps = <1860>; /* 960ps */

			rxdv-skew-ps = <420>; /* 0ps */

			rxc-skew-ps = <1680>; /* 780ps */

			reg = <3>;

		};

	};

};



&gpio0 {

	status = "okay";

};



&gpio1 {

	status = "okay";

};



&gpio2 {

	status = "okay";

};



&i2c1 {

	status = "okay";

	isl12022: isl12022@6f {

		status = "okay";

		compatible = "isil,isl12022";

		reg = <0x6f>;

	};

};



/* Following mappings are taken from arria10 socdk dts */

&mmc {

	status = "okay";

	cap-sd-highspeed;

	broken-cd;

	bus-width = <4>;

};



&osc1 {

	clock-frequency = <33330000>;

};



&uart1 {

	status = "okay";

};



&usb0 {

	status = "okay";

	dr_mode = "host";

};