Commit 8ff15a8f authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: Update DCN OPTC registers 



Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0e5916ff

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+3 −1
Original line number Original line Diff line number Diff line
@@ -1584,6 +1584,7 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) 
		dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

		dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

}

}







static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

{

{

	struct hubp *hubp = pipe_ctx->plane_res.hubp;

	struct hubp *hubp = pipe_ctx->plane_res.hubp;
@@ -1819,9 +1820,10 @@ static void program_all_pipe_in_tree( 
			dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);

			dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);

	}

	}





	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)

	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) {

		program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);

		program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);

	}

	}

}





static void dcn10_pplib_apply_display_requirements(

static void dcn10_pplib_apply_display_requirements(

	struct dc *dc,

	struct dc *dc,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h

+4 −2
Original line number Original line Diff line number Diff line
@@ -83,6 +83,8 @@ 








struct dcn_optc_registers {

struct dcn_optc_registers {

	uint32_t OTG_GLOBAL_CONTROL1;

	uint32_t OTG_GLOBAL_CONTROL2;

	uint32_t OTG_VERT_SYNC_CONTROL;

	uint32_t OTG_VERT_SYNC_CONTROL;

	uint32_t OTG_MASTER_UPDATE_MODE;

	uint32_t OTG_MASTER_UPDATE_MODE;

	uint32_t OTG_GSL_CONTROL;

	uint32_t OTG_GSL_CONTROL;
@@ -126,6 +128,7 @@ struct dcn_optc_registers { 
	uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;

	uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;

	uint32_t OPTC_INPUT_CLOCK_CONTROL;

	uint32_t OPTC_INPUT_CLOCK_CONTROL;

	uint32_t OPTC_DATA_SOURCE_SELECT;

	uint32_t OPTC_DATA_SOURCE_SELECT;

	uint32_t OPTC_MEMORY_CONFIG;

	uint32_t OPTC_INPUT_GLOBAL_CONTROL;

	uint32_t OPTC_INPUT_GLOBAL_CONTROL;

	uint32_t CONTROL;

	uint32_t CONTROL;

	uint32_t OTG_GSL_WINDOW_X;

	uint32_t OTG_GSL_WINDOW_X;
@@ -325,10 +328,9 @@ struct dcn_optc_registers { 
	type OPTC_INPUT_CLK_EN;\

	type OPTC_INPUT_CLK_EN;\

	type OPTC_INPUT_CLK_ON;\

	type OPTC_INPUT_CLK_ON;\

	type OPTC_INPUT_CLK_GATE_DIS;\

	type OPTC_INPUT_CLK_GATE_DIS;\

	type OPTC_SRC_SEL;\

	type OPTC_SEG0_SRC_SEL;\

	type OPTC_UNDERFLOW_OCCURRED_STATUS;\

	type OPTC_UNDERFLOW_OCCURRED_STATUS;\

	type OPTC_UNDERFLOW_CLEAR;\

	type OPTC_UNDERFLOW_CLEAR;\

	type OPTC_SRC_SEL;\

	type VTG0_ENABLE;\

	type VTG0_ENABLE;\

	type VTG0_FP2;\

	type VTG0_FP2;\

	type VTG0_VCOUNT_INIT;\

	type VTG0_VCOUNT_INIT;\