Commit 9026b5d5 authored by Anton Gerasimov's avatar Anton Gerasimov Committed by Greg Kroah-Hartman
Browse files

staging: fbtft: rearrange comments for readability 



Placed comments to register writes before the function calls to
eliminate long strings and make code more readable.

Signed-off-by: default avatarAnton Gerasimov <anton.gerasimov@openmailbox.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent bc573c51

drivers/staging/fbtft/fb_ili9320.c

+88 −30
Original line number Diff line number Diff line
@@ -63,43 +63,101 @@ static int init_display(struct fbtft_par *par) 
	/* Initialization sequence from ILI9320 Application Notes */



	/* *********** Start Initial Sequence ********* */

	write_reg(par, 0x00E5, 0x8000); /* Set the Vcore voltage and this setting is must. */

	write_reg(par, 0x0000, 0x0001); /* Start internal OSC. */

	write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */

	write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */

	write_reg(par, 0x0004, 0x0000); /* Resize register */

	write_reg(par, 0x0008, 0x0202); /* set the back and front porch */

	write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */

	write_reg(par, 0x000A, 0x0000); /* FMARK function */

	write_reg(par, 0x000C, 0x0000); /* RGB interface setting */

	write_reg(par, 0x000D, 0x0000); /* Frame marker Position */

	write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */

	/* Set the Vcore voltage and this setting is must. */

	write_reg(par, 0x00E5, 0x8000);



	/* Start internal OSC. */

	write_reg(par, 0x0000, 0x0001);



	/* set SS and SM bit */

	write_reg(par, 0x0001, 0x0100);



	/* set 1 line inversion */

	write_reg(par, 0x0002, 0x0700);



	/* Resize register */

	write_reg(par, 0x0004, 0x0000);



	/* set the back and front porch */

	write_reg(par, 0x0008, 0x0202);



	/* set non-display area refresh cycle */

	write_reg(par, 0x0009, 0x0000);



	/* FMARK function */

	write_reg(par, 0x000A, 0x0000);



	/* RGB interface setting */

	write_reg(par, 0x000C, 0x0000);



	/* Frame marker Position */

	write_reg(par, 0x000D, 0x0000);



	/* RGB interface polarity */

	write_reg(par, 0x000F, 0x0000);





	/* ***********Power On sequence *************** */

	write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */

	write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */

	write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */

	write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */

	mdelay(200); /* Dis-charge capacitor power voltage */

	write_reg(par, 0x0010, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */

	write_reg(par, 0x0011, 0x0031); /* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */

	/* SAP, BT[3:0], AP, DSTB, SLP, STB */

	write_reg(par, 0x0010, 0x0000);



	/* DC1[2:0], DC0[2:0], VC[2:0] */

	write_reg(par, 0x0011, 0x0007);



	/* VREG1OUT voltage */

	write_reg(par, 0x0012, 0x0000);



	/* VDV[4:0] for VCOM amplitude */

	write_reg(par, 0x0013, 0x0000);



	/* Dis-charge capacitor power voltage */

	mdelay(200);



	/* SAP, BT[3:0], AP, DSTB, SLP, STB */

	write_reg(par, 0x0010, 0x17B0);



	/* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */

	write_reg(par, 0x0011, 0x0031);

	mdelay(50);

	write_reg(par, 0x0012, 0x0138); /* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */



	/* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */

	write_reg(par, 0x0012, 0x0138);

	mdelay(50);

	write_reg(par, 0x0013, 0x1800); /* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */

	write_reg(par, 0x0029, 0x0008); /* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */



	/* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */

	write_reg(par, 0x0013, 0x1800);



	/* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */

	write_reg(par, 0x0029, 0x0008);

	mdelay(50);

	write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */

	write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */



	/* GRAM horizontal Address */

	write_reg(par, 0x0020, 0x0000);



	/* GRAM Vertical Address */

	write_reg(par, 0x0021, 0x0000);



	/* ------------------ Set GRAM area --------------- */

	write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */

	write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */

	write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */

	write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */

	write_reg(par, 0x0060, 0x2700); /* Gate Scan Line */

	write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */

	write_reg(par, 0x006A, 0x0000); /* set scrolling line */

	/* Horizontal GRAM Start Address */

	write_reg(par, 0x0050, 0x0000);



	/* Horizontal GRAM End Address */

	write_reg(par, 0x0051, 0x00EF);



	/* Vertical GRAM Start Address */

	write_reg(par, 0x0052, 0x0000);



	/* Vertical GRAM Start Address */

	write_reg(par, 0x0053, 0x013F);



	/* Gate Scan Line */

	write_reg(par, 0x0060, 0x2700);



	/* NDL,VLE, REV */

	write_reg(par, 0x0061, 0x0001);



	/* set scrolling line */

	write_reg(par, 0x006A, 0x0000);



	/* -------------- Partial Display Control --------- */

	write_reg(par, 0x0080, 0x0000);