Unverified Commit 917d5758 authored by Richard Fitzgerald's avatar Richard Fitzgerald Committed by Mark Brown
Browse files

ASoC: cs42l42: Don't set defaults for volatile registers 



Volatile registers don't need a default value.

Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
Fixes: 2c394ca7 ("ASoC: Add support for CS42L42 codec")
Link: https://lore.kernel.org/r/20211015133619.4698-5-rf@opensource.cirrus.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent d591d4b3

sound/soc/codecs/cs42l42.c

+0 −20
Original line number Diff line number Diff line
@@ -41,7 +41,6 @@ 
static const struct reg_default cs42l42_reg_defaults[] = {

	{ CS42L42_FRZ_CTL,			0x00 },

	{ CS42L42_SRC_CTL,			0x10 },

	{ CS42L42_MCLK_STATUS,			0x02 },

	{ CS42L42_MCLK_CTL,			0x02 },

	{ CS42L42_SFTRAMP_RATE,			0xA4 },

	{ CS42L42_I2C_DEBOUNCE,			0x88 },
@@ -57,11 +56,9 @@ static const struct reg_default cs42l42_reg_defaults[] = { 
	{ CS42L42_RSENSE_CTL3,			0x1B },

	{ CS42L42_TSENSE_CTL,			0x1B },

	{ CS42L42_TSRS_INT_DISABLE,		0x00 },

	{ CS42L42_TRSENSE_STATUS,		0x00 },

	{ CS42L42_HSDET_CTL1,			0x77 },

	{ CS42L42_HSDET_CTL2,			0x00 },

	{ CS42L42_HS_SWITCH_CTL,		0xF3 },

	{ CS42L42_HS_DET_STATUS,		0x00 },

	{ CS42L42_HS_CLAMP_DISABLE,		0x00 },

	{ CS42L42_MCLK_SRC_SEL,			0x00 },

	{ CS42L42_SPDIF_CLK_CFG,		0x00 },
@@ -75,18 +72,6 @@ static const struct reg_default cs42l42_reg_defaults[] = { 
	{ CS42L42_IN_ASRC_CLK,			0x00 },

	{ CS42L42_OUT_ASRC_CLK,			0x00 },

	{ CS42L42_PLL_DIV_CFG1,			0x00 },

	{ CS42L42_ADC_OVFL_STATUS,		0x00 },

	{ CS42L42_MIXER_STATUS,			0x00 },

	{ CS42L42_SRC_STATUS,			0x00 },

	{ CS42L42_ASP_RX_STATUS,		0x00 },

	{ CS42L42_ASP_TX_STATUS,		0x00 },

	{ CS42L42_CODEC_STATUS,			0x00 },

	{ CS42L42_DET_INT_STATUS1,		0x00 },

	{ CS42L42_DET_INT_STATUS2,		0x00 },

	{ CS42L42_SRCPL_INT_STATUS,		0x00 },

	{ CS42L42_VPMON_STATUS,			0x00 },

	{ CS42L42_PLL_LOCK_STATUS,		0x00 },

	{ CS42L42_TSRS_PLUG_STATUS,		0x00 },

	{ CS42L42_ADC_OVFL_INT_MASK,		0x01 },

	{ CS42L42_MIXER_INT_MASK,		0x0F },

	{ CS42L42_SRC_INT_MASK,			0x0F },
@@ -105,8 +90,6 @@ static const struct reg_default cs42l42_reg_defaults[] = { 
	{ CS42L42_PLL_CTL3,			0x10 },

	{ CS42L42_PLL_CAL_RATIO,		0x80 },

	{ CS42L42_PLL_CTL4,			0x03 },

	{ CS42L42_LOAD_DET_RCSTAT,		0x00 },

	{ CS42L42_LOAD_DET_DONE,		0x00 },

	{ CS42L42_LOAD_DET_EN,			0x00 },

	{ CS42L42_HSBIAS_SC_AUTOCTL,		0x03 },

	{ CS42L42_WAKE_CTL,			0xC0 },
@@ -115,8 +98,6 @@ static const struct reg_default cs42l42_reg_defaults[] = { 
	{ CS42L42_MISC_DET_CTL,			0x03 },

	{ CS42L42_MIC_DET_CTL1,			0x1F },

	{ CS42L42_MIC_DET_CTL2,			0x2F },

	{ CS42L42_DET_STATUS1,			0x00 },

	{ CS42L42_DET_STATUS2,			0x00 },

	{ CS42L42_DET_INT1_MASK,		0xE0 },

	{ CS42L42_DET_INT2_MASK,		0xFF },

	{ CS42L42_HS_BIAS_CTL,			0xC2 },
@@ -182,7 +163,6 @@ static const struct reg_default cs42l42_reg_defaults[] = { 
	{ CS42L42_ASP_RX_DAI1_CH2_AP_RES,	0x03 },

	{ CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,	0x00 },

	{ CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,	0x00 },

	{ CS42L42_SUB_REVID,			0x03 },

};



static bool cs42l42_readable_register(struct device *dev, unsigned int reg)