Commit 9190d4a2 authored by Brandon Syu's avatar Brandon Syu Committed by Alex Deucher
Browse files

drm/amd/display: fix mapping to non-allocated address 



[Why]
There is an issue mapping non-allocated location of memory.
It would allocate gpio registers from an array out of bounds.

[How]
Patch correct numbers of bounds for using.

Tested-by: default avatarDaniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: default avatarMartin Leung <Martin.Leung@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarBrandon Syu <Brandon.Syu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e0886e1f

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

+4 −2
Original line number Diff line number Diff line
@@ -138,7 +138,8 @@ static const struct ddc_sh_mask ddc_shift[] = { 
	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),

	DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)

};



static const struct ddc_sh_mask ddc_mask[] = {
@@ -147,7 +148,8 @@ static const struct ddc_sh_mask ddc_mask[] = { 
	DDC_MASK_SH_LIST_DCN2(_MASK, 3),

	DDC_MASK_SH_LIST_DCN2(_MASK, 4),

	DDC_MASK_SH_LIST_DCN2(_MASK, 5),

	DDC_MASK_SH_LIST_DCN2(_MASK, 6)

	DDC_MASK_SH_LIST_DCN2(_MASK, 6),

	DDC_MASK_SH_LIST_DCN2_VGA(_MASK)

};



#include "../generic_regs.h"

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

+4 −2
Original line number Diff line number Diff line
@@ -145,7 +145,8 @@ static const struct ddc_sh_mask ddc_shift[] = { 
	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),

	DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)

};



static const struct ddc_sh_mask ddc_mask[] = {
@@ -154,7 +155,8 @@ static const struct ddc_sh_mask ddc_mask[] = { 
	DDC_MASK_SH_LIST_DCN2(_MASK, 3),

	DDC_MASK_SH_LIST_DCN2(_MASK, 4),

	DDC_MASK_SH_LIST_DCN2(_MASK, 5),

	DDC_MASK_SH_LIST_DCN2(_MASK, 6)

	DDC_MASK_SH_LIST_DCN2(_MASK, 6),

	DDC_MASK_SH_LIST_DCN2_VGA(_MASK)

};



#include "../generic_regs.h"

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

+4 −2
Original line number Diff line number Diff line
@@ -149,7 +149,8 @@ static const struct ddc_sh_mask ddc_shift[] = { 
	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)

	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),

	DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)

};



static const struct ddc_sh_mask ddc_mask[] = {
@@ -158,7 +159,8 @@ static const struct ddc_sh_mask ddc_mask[] = { 
	DDC_MASK_SH_LIST_DCN2(_MASK, 3),

	DDC_MASK_SH_LIST_DCN2(_MASK, 4),

	DDC_MASK_SH_LIST_DCN2(_MASK, 5),

	DDC_MASK_SH_LIST_DCN2(_MASK, 6)

	DDC_MASK_SH_LIST_DCN2(_MASK, 6),

	DDC_MASK_SH_LIST_DCN2_VGA(_MASK)

};



#include "../generic_regs.h"

drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h

+7 −0
Original line number Diff line number Diff line
@@ -113,6 +113,13 @@ 
	(PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\

	(DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)}



#define DDC_MASK_SH_LIST_DCN2_VGA(mask_sh) \

	{DDC_MASK_SH_LIST_COMMON(mask_sh),\

	0,\

	0,\

	0,\

	0}



struct ddc_registers {

	struct gpio_registers gpio;

	uint32_t ddc_setup;