Commit 91bda9e9 authored by Chris Park's avatar Chris Park Committed by Alex Deucher
Browse files

drm/amd/display: Update panel register 



[Why]
Incorrect panel register settings are
applied for power sequence because the
register macro is not defined in resource.

[How]
Implement same register space to future
resource files.

Signed-off-by: default avatarChris Park <Chris.Park@amd.com>
Reviewed-by: default avatarJoshua Aberback <Joshua.Aberback@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7dd4f4df

drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -967,7 +967,7 @@ static const struct encoder_feature_support link_enc_feature = { 
		[id] = {\

				LE_DCN3_REG_LIST(id), \

				UNIPHY_DCN2_REG_LIST(phyid), \

				DPCS_DCN2_REG_LIST(id), \

				SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \

		}



static const struct dcn10_link_enc_registers link_enc_regs[] = {