Commit 9223cb66 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: r9a07g044: Add SPI Multi I/O Bus controller node 



Add SPI Multi I/O Bus controller node to R9A07G044 (RZ/G2L) SoC DTSI.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210928155852.32569-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 732e8ee0

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -358,6 +358,23 @@ channel@7 { 
			};

		};



		sbc: spi@10060000 {

			compatible = "renesas,r9a07g044-rpc-if",

				     "renesas,rzg2l-rpc-if";

			reg = <0 0x10060000 0 0x10000>,

			      <0 0x20000000 0 0x10000000>,

			      <0 0x10070000 0 0x10000>;

			reg-names = "regs", "dirmap", "wbuf";

			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,

				 <&cpg CPG_MOD R9A07G044_SPI_CLK>;

			resets = <&cpg R9A07G044_SPI_RST>;

			power-domains = <&cpg>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		cpg: clock-controller@11010000 {

			compatible = "renesas,r9a07g044-cpg";

			reg = <0 0x11010000 0 0x10000>;