Commit 923dcc5e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'akpm' (patches from Andrew) 

Merge misc fixes from Andrew Morton:
 "15 patches.

  Subsystems affected by this patch series: ipc, hexagon, mm (swap,
  slab-generic, kmemleak, hugetlb, kasan, damon, and highmem), and proc"

* emailed patches from Andrew Morton <akpm@linux-foundation.org>:
  proc/vmcore: fix clearing user buffer by properly using clear_user()
  kmap_local: don't assume kmap PTEs are linear arrays in memory
  mm/damon/dbgfs: fix missed use of damon_dbgfs_lock
  mm/damon/dbgfs: use '__GFP_NOWARN' for user-specified size buffer allocation
  kasan: test: silence intentional read overflow warnings
  hugetlb, userfaultfd: fix reservation restore on userfaultfd error
  hugetlb: fix hugetlb cgroup refcounting during mremap
  mm: kmemleak: slob: respect SLAB_NOLEAKTRACE flag
  hexagon: ignore vmlinux.lds
  hexagon: clean up timer-regs.h
  hexagon: export raw I/O routines for modules
  mm: emit the "free" trace report before freeing memory in kmem_cache_free()
  shm: extend forced shm destroy to support objects from several IPC nses
  ipc: WARN if trying to remove ipc object which is absent
  mm/swap.c:put_pages_list(): reinitialise the page list
parents 61564e7b c1e63117

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -1463,6 +1463,7 @@ config HIGHMEM 
	bool "High Memory Support"

	depends on MMU

	select KMAP_LOCAL

	select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY

	help

	  The address space of ARM processors is only 4 Gigabytes large

	  and it has to accommodate user address space, kernel address

arch/hexagon/include/asm/timer-regs.h

deleted100644 → 0
+0 −26
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Timer support for Hexagon

 *

 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.

 */



#ifndef _ASM_TIMER_REGS_H

#define _ASM_TIMER_REGS_H



/*  This stuff should go into a platform specific file  */

#define TCX0_CLK_RATE		19200

#define TIMER_ENABLE		0

#define TIMER_CLR_ON_MATCH	1



/*

 * 8x50 HDD Specs 5-8.  Simulator co-sim not fixed until

 * release 1.1, and then it's "adjustable" and probably not defaulted.

 */

#define RTOS_TIMER_INT		3

#ifdef CONFIG_HEXAGON_COMET

#define RTOS_TIMER_REGS_ADDR	0xAB000000UL

#endif

#define SLEEP_CLK_RATE		32000



#endif

arch/hexagon/include/asm/timex.h

+1 −2
Original line number Diff line number Diff line
@@ -7,11 +7,10 @@ 
#define _ASM_TIMEX_H



#include <asm-generic/timex.h>

#include <asm/timer-regs.h>

#include <asm/hexagon_vm.h>



/* Using TCX0 as our clock.  CLOCK_TICK_RATE scheduled to be removed. */

#define CLOCK_TICK_RATE              TCX0_CLK_RATE

#define CLOCK_TICK_RATE              19200



#define ARCH_HAS_READ_CURRENT_TIMER

arch/hexagon/kernel/.gitignore

0 → 100644
+1 −0
Original line number Diff line number Diff line 
vmlinux.lds

arch/hexagon/kernel/time.c

+10 −2
Original line number Diff line number Diff line
@@ -17,9 +17,10 @@ 
#include <linux/of_irq.h>

#include <linux/module.h>



#include <asm/timer-regs.h>

#include <asm/hexagon_vm.h>



#define TIMER_ENABLE		BIT(0)



/*

 * For the clocksource we need:

 *	pcycle frequency (600MHz)
@@ -33,6 +34,13 @@ cycles_t pcycle_freq_mhz; 
cycles_t	thread_freq_mhz;

cycles_t	sleep_clk_freq;



/*

 * 8x50 HDD Specs 5-8.  Simulator co-sim not fixed until

 * release 1.1, and then it's "adjustable" and probably not defaulted.

 */

#define RTOS_TIMER_INT		3

#define RTOS_TIMER_REGS_ADDR	0xAB000000UL



static struct resource rtos_timer_resources[] = {

	{

		.start	= RTOS_TIMER_REGS_ADDR,
@@ -80,7 +88,7 @@ static int set_next_event(unsigned long delta, struct clock_event_device *evt) 
	iowrite32(0, &rtos_timer->clear);



	iowrite32(delta, &rtos_timer->match);

	iowrite32(1 << TIMER_ENABLE, &rtos_timer->enable);

	iowrite32(TIMER_ENABLE, &rtos_timer->enable);

	return 0;

}