Commit 9248681f authored by Ashley Thomas's avatar Ashley Thomas Committed by Alex Deucher
Browse files

drm/amd/display: Source minimum HBlank support 



[Why]
Some sink devices wish to have access to the minimum
HBlank supported by the ASIC.

[How]
Make the ASIC minimum HBlank available in Source
Device information address 0x340.

Signed-off-by: default avatarAshley Thomas <Ashley.Thomas2@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2e7b43e6

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

+2 −0
Original line number Diff line number Diff line
@@ -418,6 +418,8 @@ char *dc_status_to_str(enum dc_status status) 
		return "Fail clk below minimum";

	case DC_FAIL_CLK_BELOW_CFG_REQUIRED:

		return "Fail clk below required CFG (hard_min in PPLIB)";

	case DC_NOT_SUPPORTED:

		return "The operation is not supported.";

	case DC_ERROR_UNEXPECTED:

		return "Unexpected error";

	}

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+32 −7
Original line number Diff line number Diff line
@@ -17,13 +17,13 @@ 


#define DC_LOGGER \

	link->ctx->logger



#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */



#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50



	/* maximum pre emphasis level allowed for each voltage swing level*/

static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {

		PRE_EMPHASIS_LEVEL3,

	static const enum dc_pre_emphasis

	voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,

					    PRE_EMPHASIS_LEVEL2,

					    PRE_EMPHASIS_LEVEL1,

					    PRE_EMPHASIS_DISABLED };
@@ -4372,6 +4372,7 @@ void dp_set_fec_enable(struct dc_link *link, bool enable) 
void dpcd_set_source_specific_data(struct dc_link *link)

{

	if (!link->dc->vendor_signature.is_valid) {

		enum dc_status result_write_min_hblank = DC_NOT_SUPPORTED;

		struct dpcd_amd_signature amd_signature;

		amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;

		amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
@@ -4390,6 +4391,30 @@ void dpcd_set_source_specific_data(struct dc_link *link) 
				(uint8_t *)(&amd_signature),

				sizeof(amd_signature));



		if (link->ctx->dce_version >= DCN_VERSION_2_0 &&

			link->dc->caps.min_horizontal_blanking_period != 0) {



			uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;



			result_write_min_hblank = core_link_write_dpcd(link,

				DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),

				sizeof(hblank_size));

		}

		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,

							WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,

							"result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",

							result_write_min_hblank,

							link->link_index,

							link->ctx->dce_version,

							DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,

							link->dc->caps.min_horizontal_blanking_period,

							link->dpcd_caps.branch_dev_id,

							link->dpcd_caps.branch_dev_name[0],

							link->dpcd_caps.branch_dev_name[1],

							link->dpcd_caps.branch_dev_name[2],

							link->dpcd_caps.branch_dev_name[3],

							link->dpcd_caps.branch_dev_name[4],

							link->dpcd_caps.branch_dev_name[5]);

	} else {

		core_link_write_dpcd(link, DP_SOURCE_OUI,

				link->dc->vendor_signature.data.raw,

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ struct dc_caps { 
	uint32_t dmdata_alloc_size;

	unsigned int max_cursor_size;

	unsigned int max_video_width;

	unsigned int min_horizontal_blanking_period;

	int linear_pitch_alignment;

	bool dcc_const_color;

	bool dynamic_audio;

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -1066,6 +1066,7 @@ static bool dce100_resource_construct( 
	dc->caps.i2c_speed_in_khz = 40;

	dc->caps.i2c_speed_in_khz = 40;

	dc->caps.max_cursor_size = 128;

	dc->caps.min_horizontal_blanking_period = 80;

	dc->caps.dual_link_dvi = true;

	dc->caps.disable_dp_clk_share = true;

	dc->caps.extended_aux_timeout_support = false;

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -1368,6 +1368,7 @@ static bool dce110_resource_construct( 
	dc->caps.i2c_speed_in_khz = 40;

	dc->caps.i2c_speed_in_khz_hdcp = 40;

	dc->caps.max_cursor_size = 128;

	dc->caps.min_horizontal_blanking_period = 80;

	dc->caps.is_apu = true;

	dc->caps.extended_aux_timeout_support = false;