Commit 932d8c56 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

clk: qcom: mmcc-msm8998: Properly consume GPLL0 inputs 



Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed
child of MMSS_GPLL0_DIV that's always-on. Properly representing the
former in the GCC driver makes us unable to keep doing so.

Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a
fixed .name link to keep backwards compatibility.

Reviewed-by: default avatarJeffrey Hugo <quic_jhugo@quicinc.com>
Tested-by: default avatarJeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-4-6222fbc2916b@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 9c76c5cf

drivers/clk/qcom/mmcc-msm8998.c

+8 −27
Original line number Diff line number Diff line
@@ -46,19 +46,6 @@ enum { 
	P_DPLINK,

};



static struct clk_fixed_factor gpll0_div = {

	.mult = 1,

	.div = 2,

	.hw.init = &(struct clk_init_data){

		.name = "mmss_gpll0_div",

		.parent_data = &(const struct clk_parent_data){

			.fw_name = "gpll0"

		},

		.num_parents = 1,

		.ops = &clk_fixed_factor_ops,

	},

};



static const struct clk_div_table post_div_table_fabia_even[] = {

	{ 0x0, 1 },

	{ 0x1, 2 },
@@ -354,7 +341,7 @@ static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { 
static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {

	{ .fw_name = "xo" },

	{ .fw_name = "gpll0" },

	{ .hw = &gpll0_div.hw },

	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },

};



static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
@@ -368,7 +355,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = { 
	{ .fw_name = "xo" },

	{ .hw = &mmpll0_out_even.clkr.hw },

	{ .fw_name = "gpll0" },

	{ .hw = &gpll0_div.hw },

	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },

};



static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
@@ -384,7 +371,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { 
	{ .hw = &mmpll0_out_even.clkr.hw },

	{ .hw = &mmpll1_out_even.clkr.hw },

	{ .fw_name = "gpll0" },

	{ .hw = &gpll0_div.hw },

	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },

};



static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
@@ -400,7 +387,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { 
	{ .hw = &mmpll0_out_even.clkr.hw },

	{ .hw = &mmpll5_out_even.clkr.hw },

	{ .fw_name = "gpll0" },

	{ .hw = &gpll0_div.hw },

	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },

};



static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
@@ -418,7 +405,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div 
	{ .hw = &mmpll3_out_even.clkr.hw },

	{ .hw = &mmpll6_out_even.clkr.hw },

	{ .fw_name = "gpll0" },

	{ .hw = &gpll0_div.hw },

	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },

};



static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
@@ -436,7 +423,7 @@ static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_di 
	{ .hw = &mmpll7_out_even.clkr.hw },

	{ .hw = &mmpll10_out_even.clkr.hw },

	{ .fw_name = "gpll0" },

	{ .hw = &gpll0_div.hw },

	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },

};



static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
@@ -454,7 +441,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_di 
	{ .hw = &mmpll7_out_even.clkr.hw },

	{ .hw = &mmpll10_out_even.clkr.hw },

	{ .fw_name = "gpll0" },

	{ .hw = &gpll0_div.hw },

	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },

};



static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
@@ -474,7 +461,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_g 
	{ .hw = &mmpll7_out_even.clkr.hw },

	{ .hw = &mmpll10_out_even.clkr.hw },

	{ .fw_name = "gpll0" },

	{ .hw = &gpll0_div.hw },

	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },

};



static struct clk_rcg2 byte0_clk_src = {
@@ -2544,10 +2531,6 @@ static struct clk_branch vmem_ahb_clk = { 
	},

};



static struct clk_hw *mmcc_msm8998_hws[] = {

	&gpll0_div.hw,

};



static struct gdsc video_top_gdsc = {

	.gdscr = 0x1024,

	.pd = {
@@ -2855,8 +2838,6 @@ static const struct qcom_cc_desc mmcc_msm8998_desc = { 
	.num_resets = ARRAY_SIZE(mmcc_msm8998_resets),

	.gdscs = mmcc_msm8998_gdscs,

	.num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),

	.clk_hws = mmcc_msm8998_hws,

	.num_clk_hws = ARRAY_SIZE(mmcc_msm8998_hws),

};



static const struct of_device_id mmcc_msm8998_match_table[] = {