Commit 94055304 authored by Liav Rehana's avatar Liav Rehana Committed by Vineet Gupta
Browse files

ARC: typos fix in kernel/entry-compact.S 



Signed-off-by: default avatarLiav Rehana <liavr@mellanox.com>
Signed-off-by: default avatarNoam Camus <noamca@mellanox.com>
Reviewed-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent ddf720f8

arch/arc/kernel/entry-compact.S

+11 −11
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ 
 *

 * Vineetg: Oct 2009

 *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled

 *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains

 *   out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains

 *   active (AE bit enabled).  This causes a double fault for a subseq valid

 *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.

 *   Instr Error could also cause similar scenario, so same there as well.
@@ -59,7 +59,7 @@ 
 */



#include <linux/errno.h>

#include <linux/linkage.h>	/* {EXTRY,EXIT} */

#include <linux/linkage.h>	/* {ENTRY,EXIT} */

#include <asm/entry.h>

#include <asm/irqflags.h>
@@ -80,8 +80,8 @@ 
	.align 4



/* Each entry in the vector table must occupy 2 words. Since it is a jump

 * across sections (.vector to .text) we are gauranteed that 'j somewhere'

 * will use the 'j limm' form of the intrsuction as long as somewhere is in

 * across sections (.vector to .text) we are guaranteed that 'j somewhere'

 * will use the 'j limm' form of the instruction as long as somewhere is in

 * a section other than .vector.

 */
@@ -105,13 +105,13 @@ VECTOR handle_interrupt_level1 ; Other devices 


; ******************** Exceptions **********************

VECTOR   EV_MachineCheck         ; 0x100, Fatal Machine check   (0x20)

VECTOR   EV_TLBMissI             ; 0x108, Intruction TLB miss   (0x21)

VECTOR   EV_TLBMissI             ; 0x108, Instruction TLB miss  (0x21)

VECTOR   EV_TLBMissD             ; 0x110, Data TLB miss         (0x22)

VECTOR   EV_TLBProtV             ; 0x118, Protection Violation  (0x23)

				 ;         or Misaligned Access

VECTOR   EV_PrivilegeV           ; 0x120, Privilege Violation   (0x24)

VECTOR   EV_Trap                 ; 0x128, Trap exception        (0x25)

VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)

VECTOR   EV_Extension            ; 0x130, Extn Instruction Excp (0x26)



.rept   24

VECTOR   reserved                ; Reserved Exceptions
@@ -199,7 +199,7 @@ END(handle_interrupt_level2) 


; ---------------------------------------------

; User Mode Memory Bus Error Interrupt Handler

; (Kernel mode memory errors handled via seperate exception vectors)

; (Kernel mode memory errors handled via separate exception vectors)

; ---------------------------------------------

ENTRY(mem_service)
@@ -273,7 +273,7 @@ ENTRY(EV_TLBProtV) 
	;------ (5) Type of Protection Violation? ----------

	;

	; ProtV Hardware Exception is triggered for Access Faults of 2 types

	;   -Access Violaton	: 00_23_(00|01|02|03)_00

	;   -Access Violation	: 00_23_(00|01|02|03)_00

	;			         x  r  w  r+w

	;   -Unaligned Access	: 00_23_04_00

	;
@@ -327,7 +327,7 @@ END(call_do_page_fault) 


.Lrestore_regs:



	# Interrpts are actually disabled from this point on, but will get

	# Interrupts are actually disabled from this point on, but will get

	# reenabled after we return from interrupt/exception.

	# But irq tracer needs to be told now...

	TRACE_ASM_IRQ_ENABLE
@@ -335,7 +335,7 @@ END(call_do_page_fault) 
	lr	r10, [status32]



	; Restore REG File. In case multiple Events outstanding,

	; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None

	; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None

	; Note that we use realtime STATUS32 (not pt_regs->status32) to

	; decide that.