Commit 946ca97e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2021-10-28' of... 

Merge tag 'drm-intel-fixes-2021-10-28' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

drm/i915 fixes for v5.15 final:
- Remove unconditional clflushes
- Fix oops on boot due to sync state on disabled DP encoders
- Revert backend specific data added to tracepoints
- Remove useless and incorrect memory frequence calculation

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/8735olh27y.fsf@intel.com
parents 79516af3 9a4aa3a2

drivers/gpu/drm/i915/display/intel_dp.c

+3 −0
Original line number Diff line number Diff line
@@ -1916,6 +1916,9 @@ void intel_dp_sync_state(struct intel_encoder *encoder, 
{

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



	if (!crtc_state)

		return;



	/*

	 * Don't clobber DPCD if it's been already read out during output

	 * setup (eDP) or detect.

drivers/gpu/drm/i915/gt/intel_timeline.c

+2 −2
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ intel_timeline_pin_map(struct intel_timeline *timeline) 


	timeline->hwsp_map = vaddr;

	timeline->hwsp_seqno = memset(vaddr + ofs, 0, TIMELINE_SEQNO_BYTES);

	clflush(vaddr + ofs);

	drm_clflush_virt_range(vaddr + ofs, TIMELINE_SEQNO_BYTES);



	return 0;

}
@@ -225,7 +225,7 @@ void intel_timeline_reset_seqno(const struct intel_timeline *tl) 


	memset(hwsp_seqno + 1, 0, TIMELINE_SEQNO_BYTES - sizeof(*hwsp_seqno));

	WRITE_ONCE(*hwsp_seqno, tl->seqno);

	clflush(hwsp_seqno);

	drm_clflush_virt_range(hwsp_seqno, TIMELINE_SEQNO_BYTES);

}



void intel_timeline_enter(struct intel_timeline *tl)

drivers/gpu/drm/i915/i915_reg.h

+0 −8
Original line number Diff line number Diff line
@@ -11048,12 +11048,6 @@ enum skl_power_gate { 
#define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)

#define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)



#define BXT_P_CR_MC_BIOS_REQ_0_0_0	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)

#define  BXT_REQ_DATA_MASK			0x3F

#define  BXT_DRAM_CHANNEL_ACTIVE_SHIFT		12

#define  BXT_DRAM_CHANNEL_ACTIVE_MASK		(0xF << 12)

#define  BXT_MEMORY_FREQ_MULTIPLIER_HZ		133333333



#define BXT_D_CR_DRP0_DUNIT8			0x1000

#define BXT_D_CR_DRP0_DUNIT9			0x1200

#define  BXT_D_CR_DRP0_DUNIT_START		8
@@ -11084,9 +11078,7 @@ enum skl_power_gate { 
#define  BXT_DRAM_TYPE_LPDDR4			(0x2 << 22)

#define  BXT_DRAM_TYPE_DDR4			(0x4 << 22)



#define SKL_MEMORY_FREQ_MULTIPLIER_HZ		266666666

#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)

#define  SKL_REQ_DATA_MASK			(0xF << 0)

#define  DG1_GEAR_TYPE				REG_BIT(16)



#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)

drivers/gpu/drm/i915/i915_trace.h

+2 −5
Original line number Diff line number Diff line
@@ -794,7 +794,6 @@ DECLARE_EVENT_CLASS(i915_request, 
	    TP_STRUCT__entry(

			     __field(u32, dev)

			     __field(u64, ctx)

			     __field(u32, guc_id)

			     __field(u16, class)

			     __field(u16, instance)

			     __field(u32, seqno)
@@ -805,16 +804,14 @@ DECLARE_EVENT_CLASS(i915_request, 
			   __entry->dev = rq->engine->i915->drm.primary->index;

			   __entry->class = rq->engine->uabi_class;

			   __entry->instance = rq->engine->uabi_instance;

			   __entry->guc_id = rq->context->guc_id;

			   __entry->ctx = rq->fence.context;

			   __entry->seqno = rq->fence.seqno;

			   __entry->tail = rq->tail;

			   ),



	    TP_printk("dev=%u, engine=%u:%u, guc_id=%u, ctx=%llu, seqno=%u, tail=%u",

	    TP_printk("dev=%u, engine=%u:%u, ctx=%llu, seqno=%u, tail=%u",

		      __entry->dev, __entry->class, __entry->instance,

		      __entry->guc_id, __entry->ctx, __entry->seqno,

		      __entry->tail)

		      __entry->ctx, __entry->seqno, __entry->tail)

);



DEFINE_EVENT(i915_request, i915_request_add,

drivers/gpu/drm/i915/intel_dram.c

+2 −28
Original line number Diff line number Diff line
@@ -244,7 +244,6 @@ static int 
skl_get_dram_info(struct drm_i915_private *i915)

{

	struct dram_info *dram_info = &i915->dram_info;

	u32 mem_freq_khz, val;

	int ret;



	dram_info->type = skl_get_dram_type(i915);
@@ -255,17 +254,6 @@ skl_get_dram_info(struct drm_i915_private *i915) 
	if (ret)

		return ret;



	val = intel_uncore_read(&i915->uncore,

				SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);

	mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *

				    SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);



	if (dram_info->num_channels * mem_freq_khz == 0) {

		drm_info(&i915->drm,

			 "Couldn't get system memory bandwidth\n");

		return -EINVAL;

	}



	return 0;

}
@@ -350,24 +338,10 @@ static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val) 
static int bxt_get_dram_info(struct drm_i915_private *i915)

{

	struct dram_info *dram_info = &i915->dram_info;

	u32 dram_channels;

	u32 mem_freq_khz, val;

	u8 num_active_channels, valid_ranks = 0;

	u32 val;

	u8 valid_ranks = 0;

	int i;



	val = intel_uncore_read(&i915->uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0);

	mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *

				    BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);



	dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;

	num_active_channels = hweight32(dram_channels);



	if (mem_freq_khz * num_active_channels == 0) {

		drm_info(&i915->drm,

			 "Couldn't get system memory bandwidth\n");

		return -EINVAL;

	}



	/*

	 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.

	 */