Commit 9535a86a authored by Shiwu Zhang's avatar Shiwu Zhang Committed by Alex Deucher
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drm/amdgpu: bypass bios dependent operations



Since bios reading does not work currently so just bypass all operations
related to bios

v2: hardcode the vram info for APP_APU case (hawking)
v3: correct the vram_width with channel number * channel size (lijo)

Signed-off-by: default avatarShiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: default avatarYang Wang <kevinyang.wang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cfdce594
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+41 −25
Original line number Diff line number Diff line
@@ -1389,6 +1389,15 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
	return 0;
}

static bool amdgpu_device_read_bios(struct amdgpu_device *adev)
{
	if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU)) {
		return false;
	}

	return true;
}

/*
 * GPU helpers function.
 */
@@ -1408,6 +1417,9 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev)
	if (amdgpu_sriov_vf(adev))
		return false;

	if (!amdgpu_device_read_bios(adev))
		return false;

	if (amdgpu_passthrough(adev)) {
		/* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
		 * some old smc fw still need driver do vPost otherwise gpu hang, while
@@ -2318,6 +2330,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
				return r;

			/* Read BIOS */
			if (amdgpu_device_read_bios(adev)) {
				if (!amdgpu_get_bios(adev))
					return -EINVAL;

@@ -2327,6 +2340,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
					amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
					return r;
				}
			}

			/*get pf2vf msg info at it's earliest time*/
			if (amdgpu_sriov_vf(adev))
@@ -3945,6 +3959,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
		}
	}

	if (adev->bios) {
		if (adev->is_atom_fw) {
			/* Initialize clocks */
			r = amdgpu_atomfirmware_get_clock_info(adev);
@@ -3965,6 +3980,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
			if (!amdgpu_device_has_dc_support(adev))
				amdgpu_atombios_i2c_init(adev);
		}
	}

fence_driver_init:
	/* Fence driver */
+5 −2
Original line number Diff line number Diff line
@@ -1696,7 +1696,7 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
	uint32_t reserve_size = 0;
	int ret;

	if (!amdgpu_sriov_vf(adev)) {
	if (adev->bios && !amdgpu_sriov_vf(adev)) {
		if (amdgpu_atomfirmware_mem_training_supported(adev))
			mem_train_support = true;
		else
@@ -1713,7 +1713,10 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
	if (adev->bios)
		reserve_size =
			amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
	if (!reserve_size)

	if (!adev->bios && adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3))
		reserve_size = max(reserve_size, (uint32_t)280 << 20);
	else if (!reserve_size)
		reserve_size = DISCOVERY_TMR_OFFSET;

	if (mem_train_support) {
+39 −24
Original line number Diff line number Diff line
@@ -2010,6 +2010,20 @@ static int gmc_v9_0_sw_init(void *handle)

	spin_lock_init(&adev->gmc.invalidate_lock);

	if (!(adev->bios) || adev->gmc.is_app_apu) {
		if (adev->flags & AMD_IS_APU) {
			if (adev->gmc.is_app_apu) {
				adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
				adev->gmc.vram_width = 128 * 64;
			} else {
				adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
				adev->gmc.vram_width = 64 * 64;
			}
		} else {
			adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
			adev->gmc.vram_width = 128 * 64;
		}
	} else {
		r = amdgpu_atomfirmware_get_vram_info(adev,
			&vram_width, &vram_type, &vram_vendor);
		if (amdgpu_sriov_vf(adev))
@@ -2038,6 +2052,7 @@ static int gmc_v9_0_sw_init(void *handle)

		adev->gmc.vram_type = vram_type;
		adev->gmc.vram_vendor = vram_vendor;
	}
	switch (adev->ip_versions[GC_HWIP][0]) {
	case IP_VERSION(9, 1, 0):
	case IP_VERSION(9, 2, 2):