Commit 95a212bb authored by Giovanni Cabiddu's avatar Giovanni Cabiddu Committed by Herbert Xu
Browse files

crypto: qat - abstract build ring base 



Abstract the implementation of BUILD_RING_BASE_ADDR.

This is in preparation for the introduction of the qat_4xxx driver since
the value of the ring base differs between QAT GEN2 and QAT GEN4
devices.

Signed-off-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: default avatarWojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: default avatarMaksim Lukoshkov <maksim.lukoshkov@intel.com>
Reviewed-by: default avatarFiona Trahe <fiona.trahe@intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 070a34c9

drivers/crypto/qat/qat_common/adf_accel_devices.h

+1 −0
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@ struct admin_info { 
};



struct adf_hw_csr_ops {

	u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size);

	u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,

				  u32 ring);

	void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,

drivers/crypto/qat/qat_common/adf_gen2_hw_data.c

+6 −0
Original line number Diff line number Diff line
@@ -55,6 +55,11 @@ void adf_gen2_get_arb_info(struct arb_info *arb_info) 
}

EXPORT_SYMBOL_GPL(adf_gen2_get_arb_info);



static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)

{

	return BUILD_RING_BASE_ADDR(addr, size);

}



static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)

{

	return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
@@ -124,6 +129,7 @@ static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank, 


void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)

{

	csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;

	csr_ops->read_csr_ring_head = read_csr_ring_head;

	csr_ops->write_csr_ring_head = write_csr_ring_head;

	csr_ops->read_csr_ring_tail = read_csr_ring_tail;

drivers/crypto/qat/qat_common/adf_gen2_hw_data.h

+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ 
#define ADF_RING_CSR_INT_COL_CTL_ENABLE	0x80000000

#define ADF_RING_BUNDLE_SIZE		0x1000



#define BUILD_RING_BASE_ADDR(addr, size) \

	(((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size)))

#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \

	ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

		   ADF_RING_CSR_RING_HEAD + ((ring) << 2))

drivers/crypto/qat/qat_common/adf_transport.c

+3 −1
Original line number Diff line number Diff line
@@ -180,7 +180,9 @@ static int adf_init_ring(struct adf_etr_ring_data *ring) 
	else

		adf_configure_rx_ring(ring);



	ring_base = BUILD_RING_BASE_ADDR(ring->dma_addr, ring->ring_size);

	ring_base = csr_ops->build_csr_ring_base_addr(ring->dma_addr,

						      ring->ring_size);



	csr_ops->write_csr_ring_base(ring->bank->csr_addr,

				     ring->bank->bank_number, ring->ring_number,

				     ring_base);

drivers/crypto/qat/qat_common/adf_transport_access_macros.h

+0 −2
Original line number Diff line number Diff line
@@ -56,6 +56,4 @@ 
	((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM)	\

	| (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) \

	| size)

#define BUILD_RING_BASE_ADDR(addr, size) \

	((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size))

#endif