Commit 973fb5e1 authored by Michael Walle's avatar Michael Walle Committed by Shawn Guo
Browse files

arm64: dts: ls1046a: use constants in the clockgen phandle 



Now that we have constants, use them. This is just a mechanical change.

Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 7525022d

arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

+48 −25
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
 * Mingkai Hu <mingkai.hu@nxp.com>

 */



#include <dt-bindings/clock/fsl,qoriq-clockgen.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/thermal/thermal.h>
@@ -39,7 +40,7 @@ cpu0: cpu@0 { 
			device_type = "cpu";

			compatible = "arm,cortex-a72";

			reg = <0x0>;

			clocks = <&clockgen 1 0>;

			clocks = <&clockgen QORIQ_CLK_CMUX 0>;

			next-level-cache = <&l2>;

			cpu-idle-states = <&CPU_PH20>;

			#cooling-cells = <2>;
@@ -49,7 +50,7 @@ cpu1: cpu@1 { 
			device_type = "cpu";

			compatible = "arm,cortex-a72";

			reg = <0x1>;

			clocks = <&clockgen 1 0>;

			clocks = <&clockgen QORIQ_CLK_CMUX 0>;

			next-level-cache = <&l2>;

			cpu-idle-states = <&CPU_PH20>;

			#cooling-cells = <2>;
@@ -59,7 +60,7 @@ cpu2: cpu@2 { 
			device_type = "cpu";

			compatible = "arm,cortex-a72";

			reg = <0x2>;

			clocks = <&clockgen 1 0>;

			clocks = <&clockgen QORIQ_CLK_CMUX 0>;

			next-level-cache = <&l2>;

			cpu-idle-states = <&CPU_PH20>;

			#cooling-cells = <2>;
@@ -69,7 +70,7 @@ cpu3: cpu@3 { 
			device_type = "cpu";

			compatible = "arm,cortex-a72";

			reg = <0x3>;

			clocks = <&clockgen 1 0>;

			clocks = <&clockgen QORIQ_CLK_CMUX 0>;

			next-level-cache = <&l2>;

			cpu-idle-states = <&CPU_PH20>;

			#cooling-cells = <2>;
@@ -295,7 +296,10 @@ qspi: spi@1550000 { 
			reg-names = "QuadSPI", "QuadSPI-memory";

			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "qspi_en", "qspi";

			clocks = <&clockgen 4 1>, <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			status = "disabled";

		};
@@ -303,7 +307,7 @@ esdhc: esdhc@1560000 { 
			compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";

			reg = <0x0 0x1560000 0x0 0x10000>;

			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 2 1>;

			clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;

			voltage-ranges = <1800 1800 3300 3300>;

			sdhci,auto-cmd12;

			big-endian;
@@ -479,7 +483,8 @@ dspi: spi@2100000 { 
			reg = <0x0 0x2100000 0x0 0x10000>;

			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "dspi";

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			spi-num-chipselects = <5>;

			big-endian;

			status = "disabled";
@@ -491,7 +496,8 @@ i2c0: i2c@2180000 { 
			#size-cells = <0>;

			reg = <0x0 0x2180000 0x0 0x10000>;

			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			dmas = <&edma0 1 39>,

			       <&edma0 1 38>;

			dma-names = "tx", "rx";
@@ -504,7 +510,8 @@ i2c1: i2c@2190000 { 
			#size-cells = <0>;

			reg = <0x0 0x2190000 0x0 0x10000>;

			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			status = "disabled";

		};
@@ -514,7 +521,8 @@ i2c2: i2c@21a0000 { 
			#size-cells = <0>;

			reg = <0x0 0x21a0000 0x0 0x10000>;

			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			status = "disabled";

		};
@@ -524,7 +532,8 @@ i2c3: i2c@21b0000 { 
			#size-cells = <0>;

			reg = <0x0 0x21b0000 0x0 0x10000>;

			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			status = "disabled";

		};
@@ -532,7 +541,8 @@ duart0: serial@21c0500 { 
			compatible = "fsl,ns16550", "ns16550a";

			reg = <0x00 0x21c0500 0x0 0x100>;

			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			status = "disabled";

		};
@@ -540,7 +550,8 @@ duart1: serial@21c0600 { 
			compatible = "fsl,ns16550", "ns16550a";

			reg = <0x00 0x21c0600 0x0 0x100>;

			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			status = "disabled";

		};
@@ -548,7 +559,8 @@ duart2: serial@21d0500 { 
			compatible = "fsl,ns16550", "ns16550a";

			reg = <0x0 0x21d0500 0x0 0x100>;

			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			status = "disabled";

		};
@@ -556,7 +568,8 @@ duart3: serial@21d0600 { 
			compatible = "fsl,ns16550", "ns16550a";

			reg = <0x0 0x21d0600 0x0 0x100>;

			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			status = "disabled";

		};
@@ -604,7 +617,8 @@ lpuart0: serial@2950000 { 
			compatible = "fsl,ls1021a-lpuart";

			reg = <0x0 0x2950000 0x0 0x1000>;

			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 0>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(1)>;

			clock-names = "ipg";

			status = "disabled";

		};
@@ -613,7 +627,8 @@ lpuart1: serial@2960000 { 
			compatible = "fsl,ls1021a-lpuart";

			reg = <0x0 0x2960000 0x0 0x1000>;

			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			clock-names = "ipg";

			status = "disabled";

		};
@@ -622,7 +637,8 @@ lpuart2: serial@2970000 { 
			compatible = "fsl,ls1021a-lpuart";

			reg = <0x0 0x2970000 0x0 0x1000>;

			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			clock-names = "ipg";

			status = "disabled";

		};
@@ -631,7 +647,8 @@ lpuart3: serial@2980000 { 
			compatible = "fsl,ls1021a-lpuart";

			reg = <0x0 0x2980000 0x0 0x1000>;

			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			clock-names = "ipg";

			status = "disabled";

		};
@@ -640,7 +657,8 @@ lpuart4: serial@2990000 { 
			compatible = "fsl,ls1021a-lpuart";

			reg = <0x0 0x2990000 0x0 0x1000>;

			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			clock-names = "ipg";

			status = "disabled";

		};
@@ -649,7 +667,8 @@ lpuart5: serial@29a0000 { 
			compatible = "fsl,ls1021a-lpuart";

			reg = <0x0 0x29a0000 0x0 0x1000>;

			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			clock-names = "ipg";

			status = "disabled";

		};
@@ -658,7 +677,8 @@ wdog0: watchdog@2ad0000 { 
			compatible = "fsl,imx21-wdt";

			reg = <0x0 0x2ad0000 0x0 0x10000>;

			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			big-endian;

		};
@@ -674,8 +694,10 @@ edma0: edma@2c00000 { 
			dma-channels = <32>;

			big-endian;

			clock-names = "dmamux0", "dmamux1";

			clocks = <&clockgen 4 1>,

				 <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

		};



		usb0: usb@2f00000 {
@@ -714,7 +736,8 @@ sata: sata@3200000 { 
				<0x0 0x20140520 0x0 0x4>;

			reg-names = "ahci", "sata-ecc";

			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

		};



		msi1: msi-controller@1580000 {