Loading arch/arm/boot/dts/stm32h743.dtsi +10 −10 Original line number Diff line number Diff line Loading @@ -59,13 +59,11 @@ timer_clk: timer-clk { }; soc { usart1: serial@40011000 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; clocks = <&timer_clk>; }; usart2: serial@40004400 { Loading @@ -76,11 +74,13 @@ usart2: serial@40004400 { clocks = <&timer_clk>; }; timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; usart1: serial@40011000 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; clocks = <&timer_clk>; }; }; }; Loading Loading
arch/arm/boot/dts/stm32h743.dtsi +10 −10 Original line number Diff line number Diff line Loading @@ -59,13 +59,11 @@ timer_clk: timer-clk { }; soc { usart1: serial@40011000 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; clocks = <&timer_clk>; }; usart2: serial@40004400 { Loading @@ -76,11 +74,13 @@ usart2: serial@40004400 { clocks = <&timer_clk>; }; timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; usart1: serial@40011000 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; clocks = <&timer_clk>; }; }; }; Loading