Commit 97f136ec authored by Fabio M. De Francesco's avatar Fabio M. De Francesco Committed by Greg Kroah-Hartman
Browse files

staging: rtl8723bs: include: Fix misspelled words in comments 



Correct misspelled words in comments of several files. Issue (largely)
detected by checkpatch.pl.

Signed-off-by: default avatarFabio M. De Francesco <fmdefrancesco@gmail.com>
Link: https://lore.kernel.org/r/20210411110458.15955-3-fmdefrancesco@gmail.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 90b69822

drivers/staging/rtl8723bs/include/Hal8192CPhyReg.h

+4 −4
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
/*--------------------------Define Parameters-------------------------------*/



/*  */

/*        8192S Regsiter offset definition */

/*        8192S Register offset definition */

/*  */



/*  */
@@ -43,7 +43,7 @@ 
/*  2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */

/*  3. RF register 0x00-2E */

/*  4. Bit Mask for BB/RF register */

/*  5. Other defintion for BB/RF R/W */

/*  5. Other definition for BB/RF R/W */

/*  */
@@ -137,7 +137,7 @@ 
#define		rFPGA0_AnalogParameter3		0x888	/*  Useless now */

#define		rFPGA0_AnalogParameter4		0x88c



#define		rFPGA0_XA_LSSIReadBack		0x8a0	/*  Tranceiver LSSI Readback */

#define		rFPGA0_XA_LSSIReadBack		0x8a0	/*  Transceiver LSSI Readback */

#define		rFPGA0_XB_LSSIReadBack		0x8a4

#define		rFPGA0_XC_LSSIReadBack		0x8a8

#define		rFPGA0_XD_LSSIReadBack		0x8ac
@@ -206,7 +206,7 @@ 
#define		rOFDM0_TRSWIsolation		0xc0c



#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */

#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imblance matrix */

#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */

#define		rOFDM0_XBRxAFE				0xc18

#define		rOFDM0_XBRxIQImbalance		0xc1c

#define		rOFDM0_XCRxAFE				0xc20

drivers/staging/rtl8723bs/include/basic_types.h

+1 −1
Original line number Diff line number Diff line
@@ -187,7 +187,7 @@ 
		); \

}



/*  Get the N-bytes aligment offset from the current length */

/*  Get the N-bytes alignent offset from the current length */

#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))



#define TEST_FLAG(__Flag, __testFlag)		(((__Flag) & (__testFlag)) != 0)

drivers/staging/rtl8723bs/include/drv_types.h

+1 −1
Original line number Diff line number Diff line
@@ -424,7 +424,7 @@ struct adapter { 
	/* 	The driver will show up the desired channel number when this flag is 1. */

	u8 bNotifyChannelChange;



	/* pbuddystruct adapter is used only in  two inteface case, (iface_nums =2 in struct dvobj_priv) */

	/* pbuddystruct adapter is used only in two interface case, (iface_nums =2 in struct dvobj_priv) */

	/* PRIMARY ADAPTER's buddy is SECONDARY_ADAPTER */

	/* SECONDARY_ADAPTER's buddy is PRIMARY_ADAPTER */

	/* for iface_id > SECONDARY_ADAPTER(IFACE_ID1), refer to padapters[iface_id]  in struct dvobj_priv */

drivers/staging/rtl8723bs/include/hal_com.h

+1 −1
Original line number Diff line number Diff line
@@ -158,7 +158,7 @@ 
(rate == DESC_RATEVHTSS2MCS6) ? "VHTSS2MCS6" : \

(rate == DESC_RATEVHTSS2MCS7) ? "VHTSS2MCS7" : \

(rate == DESC_RATEVHTSS2MCS8) ? "VHTSS2MCS8" : \

(rate == DESC_RATEVHTSS2MCS9) ? "VHTSS2MCS9" : "UNKNOW"

(rate == DESC_RATEVHTSS2MCS9) ? "VHTSS2MCS9" : "UNKNOWN"





enum{

drivers/staging/rtl8723bs/include/hal_com_reg.h

+17 −17
Original line number Diff line number Diff line
@@ -768,14 +768,14 @@ Default: 00b. 
#define IMR_BCNDMAINT3			BIT28		/*  Beacon DMA Interrupt 3 */

#define IMR_BCNDMAINT2			BIT27		/*  Beacon DMA Interrupt 2 */

#define IMR_BCNDMAINT1			BIT26		/*  Beacon DMA Interrupt 1 */

#define IMR_BCNDOK8				BIT25		/*  Beacon Queue DMA OK Interrup 8 */

#define IMR_BCNDOK7				BIT24		/*  Beacon Queue DMA OK Interrup 7 */

#define IMR_BCNDOK6				BIT23		/*  Beacon Queue DMA OK Interrup 6 */

#define IMR_BCNDOK5				BIT22		/*  Beacon Queue DMA OK Interrup 5 */

#define IMR_BCNDOK4				BIT21		/*  Beacon Queue DMA OK Interrup 4 */

#define IMR_BCNDOK3				BIT20		/*  Beacon Queue DMA OK Interrup 3 */

#define IMR_BCNDOK2				BIT19		/*  Beacon Queue DMA OK Interrup 2 */

#define IMR_BCNDOK1				BIT18		/*  Beacon Queue DMA OK Interrup 1 */

#define IMR_BCNDOK8				BIT25		/*  Beacon Queue DMA OK Interrupt 8 */

#define IMR_BCNDOK7				BIT24		/*  Beacon Queue DMA OK Interrupt 7 */

#define IMR_BCNDOK6				BIT23		/*  Beacon Queue DMA OK Interrupt 6 */

#define IMR_BCNDOK5				BIT22		/*  Beacon Queue DMA OK Interrupt 5 */

#define IMR_BCNDOK4				BIT21		/*  Beacon Queue DMA OK Interrupt 4 */

#define IMR_BCNDOK3				BIT20		/*  Beacon Queue DMA OK Interrupt 3 */

#define IMR_BCNDOK2				BIT19		/*  Beacon Queue DMA OK Interrupt 2 */

#define IMR_BCNDOK1				BIT18		/*  Beacon Queue DMA OK Interrupt 1 */

#define IMR_TIMEOUT2			BIT17		/*  Timeout interrupt 2 */

#define IMR_TIMEOUT1			BIT16		/*  Timeout interrupt 1 */

#define IMR_TXFOVW				BIT15		/*  Transmit FIFO Overflow */
@@ -784,9 +784,9 @@ Default: 00b. 
#define IMR_RXFOVW				BIT12		/*  Receive FIFO Overflow */

#define IMR_RDU					BIT11		/*  Receive Descriptor Unavailable */

#define IMR_ATIMEND				BIT10		/*  For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */

#define IMR_BDOK				BIT9		/*  Beacon Queue DMA OK Interrup */

#define IMR_BDOK				BIT9		/*  Beacon Queue DMA OK Interrupt */

#define IMR_HIGHDOK				BIT8		/*  High Queue DMA OK Interrupt */

#define IMR_TBDOK				BIT7		/*  Transmit Beacon OK interrup */

#define IMR_TBDOK				BIT7		/*  Transmit Beacon OK interrupt */

#define IMR_MGNTDOK			BIT6		/*  Management Queue DMA OK Interrupt */

#define IMR_TBDER				BIT5		/*  For 92C, Transmit Beacon Error Interrupt */

#define IMR_BKDOK				BIT4		/*  AC_BK DMA OK Interrupt */
@@ -956,13 +956,13 @@ Default: 00b. 
#define IMR_BCNDMAINT3_88E		BIT23		/*  Beacon DMA Interrupt 3 */

#define IMR_BCNDMAINT2_88E		BIT22		/*  Beacon DMA Interrupt 2 */

#define IMR_BCNDMAINT1_88E		BIT21		/*  Beacon DMA Interrupt 1 */

#define IMR_BCNDOK7_88E			BIT20		/*  Beacon Queue DMA OK Interrup 7 */

#define IMR_BCNDOK6_88E			BIT19		/*  Beacon Queue DMA OK Interrup 6 */

#define IMR_BCNDOK5_88E			BIT18		/*  Beacon Queue DMA OK Interrup 5 */

#define IMR_BCNDOK4_88E			BIT17		/*  Beacon Queue DMA OK Interrup 4 */

#define IMR_BCNDOK3_88E			BIT16		/*  Beacon Queue DMA OK Interrup 3 */

#define IMR_BCNDOK2_88E			BIT15		/*  Beacon Queue DMA OK Interrup 2 */

#define IMR_BCNDOK1_88E			BIT14		/*  Beacon Queue DMA OK Interrup 1 */

#define IMR_BCNDOK7_88E			BIT20		/*  Beacon Queue DMA OK Interrupt 7 */

#define IMR_BCNDOK6_88E			BIT19		/*  Beacon Queue DMA OK Interrupt 6 */

#define IMR_BCNDOK5_88E			BIT18		/*  Beacon Queue DMA OK Interrupt 5 */

#define IMR_BCNDOK4_88E			BIT17		/*  Beacon Queue DMA OK Interrupt 4 */

#define IMR_BCNDOK3_88E			BIT16		/*  Beacon Queue DMA OK Interrupt 3 */

#define IMR_BCNDOK2_88E			BIT15		/*  Beacon Queue DMA OK Interrupt 2 */

#define IMR_BCNDOK1_88E			BIT14		/*  Beacon Queue DMA OK Interrupt 1 */

#define IMR_ATIMEND_E_88E			BIT13		/*  ATIM Window End Extension for Win7 */

#define IMR_TXERR_88E				BIT11		/*  Tx Error Flag Interrupt Status, write 1 clear. */

#define IMR_RXERR_88E				BIT10		/*  Rx Error Flag INT Status, Write 1 clear */