Commit 985af6f7 authored by Marcin Tomczak's avatar Marcin Tomczak Committed by James Bottomley
Browse files

[SCSI] isci: change sas phy timeouts from 54us to 59us 



Need the following workaround in the driver for interoperability with
the older Intel SSD drives and any other SATA drive that may exhibit the
same behavior. This is a corner case where SCU speed is limited to
either 3G or 1.5G and the drive has a period of DC idle when it switches
speed during SATA speed negotiation. Workaround :change PHYTOV[31:24]
from 0x36 to 0x3B.

Signed-off-by: default avatarMarcin Tomczak <marcin.tomczak@intel.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent ee33e2b7

drivers/scsi/isci/phy.c

+13 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ sci_phy_link_layer_initialization(struct isci_phy *iphy, 
	u32 parity_count = 0;

	u32 llctl, link_rate;

	u32 clksm_value = 0;

	u32 sp_timeouts = 0;



	iphy->link_layer_registers = reg;
@@ -211,6 +212,18 @@ sci_phy_link_layer_initialization(struct isci_phy *iphy, 
	llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate);

	writel(llctl, &iphy->link_layer_registers->link_layer_control);



	sp_timeouts = readl(&iphy->link_layer_registers->sas_phy_timeouts);



	/* Clear the default 0x36 (54us) RATE_CHANGE timeout value. */

	sp_timeouts &= ~SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0xFF);



	/* Set RATE_CHANGE timeout value to 0x3B (59us).  This ensures SCU can

	 * lock with 3Gb drive when SCU max rate is set to 1.5Gb.

	 */

	sp_timeouts |= SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0x3B);



	writel(sp_timeouts, &iphy->link_layer_registers->sas_phy_timeouts);



	if (is_a2(ihost->pdev)) {

		/* Program the max ARB time for the PHY to 700us so we inter-operate with

		 * the PMC expander which shuts down PHYs if the expander PHY generates too

drivers/scsi/isci/registers.h

+12 −0
Original line number Diff line number Diff line
@@ -1299,6 +1299,18 @@ struct scu_transport_layer_registers { 
#define SCU_AFE_XCVRCR_OFFSET       0x00DC

#define SCU_AFE_LUTCR_OFFSET        0x00E0



#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_SHIFT          (0UL)

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_MASK           (0x000000FFUL)

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_SHIFT                 (8UL)

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_MASK                  (0x0000FF00UL)

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_SHIFT         (16UL)

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_MASK          (0x00FF0000UL)

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_SHIFT              (24UL)

#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_MASK               (0xFF000000UL)



#define SCU_SAS_PHYTOV_GEN_VAL(name, value) \

	SCU_GEN_VALUE(SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_##name, value)



#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT                  (0)

#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK                   (0x00000003)

#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1                   (0)