Loading drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h +1 −1 Original line number Diff line number Diff line #ifndef __NVKM_BSP_H__ #define __NVKM_BSP_H__ #include <engine/xtensa.h> extern struct nvkm_oclass g84_bsp_oclass; int g84_bsp_new(struct nvkm_device *, int, struct nvkm_engine **); #endif drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h +1 −1 Original line number Diff line number Diff line #ifndef __NVKM_VP_H__ #define __NVKM_VP_H__ #include <engine/xtensa.h> extern struct nvkm_oclass g84_vp_oclass; int g84_vp_new(struct nvkm_device *, int, struct nvkm_engine **); #endif drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h +8 −18 Original line number Diff line number Diff line Loading @@ -4,30 +4,20 @@ #include <core/engine.h> struct nvkm_xtensa { struct nvkm_engine engine; const struct nvkm_xtensa_func *func; u32 addr; struct nvkm_engine engine; struct nvkm_memory *gpu_fw; u32 fifo_val; u32 unkd28; }; int nvkm_xtensa_new_(const struct nvkm_xtensa_func *, struct nvkm_device *, int index, bool enable, u32 addr, struct nvkm_engine **); struct nvkm_xtensa_func { void (*init)(struct nvkm_xtensa *); u32 pmc_enable; u32 fifo_val; u32 unkd28; struct nvkm_sclass sclass[]; }; #define nvkm_xtensa_create(p,e,c,b,d,i,f,r) \ nvkm_xtensa_create_((p), (e), (c), (b), (d), (i), (f), \ sizeof(**r),(void **)r) int nvkm_xtensa_create_(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, u32, bool, const char *, const char *, int, void **); #define _nvkm_xtensa_dtor _nvkm_engine_dtor int _nvkm_xtensa_init(struct nvkm_object *); int _nvkm_xtensa_fini(struct nvkm_object *, bool); #endif drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c +8 −30 Original line number Diff line number Diff line Loading @@ -26,41 +26,19 @@ #include <nvif/class.h> static const struct nvkm_xtensa_func g84_bsp_func = { g84_bsp = { .pmc_enable = 0x04008000, .fifo_val = 0x1111, .unkd28 = 0x90044, .sclass = { { -1, -1, NV74_BSP }, {} } }; static int g84_bsp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) int g84_bsp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { struct nvkm_xtensa *bsp; int ret; ret = nvkm_xtensa_create(parent, engine, oclass, 0x103000, true, "PBSP", "bsp", &bsp); *pobject = nv_object(bsp); if (ret) return ret; bsp->func = &g84_bsp_func; nv_subdev(bsp)->unit = 0x04008000; bsp->fifo_val = 0x1111; bsp->unkd28 = 0x90044; return 0; return nvkm_xtensa_new_(&g84_bsp, device, index, true, 0x103000, pengine); } struct nvkm_oclass g84_bsp_oclass = { .handle = NV_ENGINE(BSP, 0x84), .ofuncs = &(struct nvkm_ofuncs) { .ctor = g84_bsp_ctor, .dtor = _nvkm_xtensa_dtor, .init = _nvkm_xtensa_init, .fini = _nvkm_xtensa_fini, }, }; drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +12 −12 Original line number Diff line number Diff line Loading @@ -897,7 +897,7 @@ nv84_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .cipher = g84_cipher_new, // .disp = g84_disp_new, // .dma = nv50_dma_new, Loading @@ -906,7 +906,7 @@ nv84_chipset = { // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, // .vp = g84_vp_new, .vp = g84_vp_new, }; static const struct nvkm_device_chip Loading @@ -928,7 +928,7 @@ nv86_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .cipher = g84_cipher_new, // .disp = g84_disp_new, // .dma = nv50_dma_new, Loading @@ -937,7 +937,7 @@ nv86_chipset = { // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, // .vp = g84_vp_new, .vp = g84_vp_new, }; static const struct nvkm_device_chip Loading @@ -959,7 +959,7 @@ nv92_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .cipher = g84_cipher_new, // .disp = g84_disp_new, // .dma = nv50_dma_new, Loading @@ -968,7 +968,7 @@ nv92_chipset = { // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, // .vp = g84_vp_new, .vp = g84_vp_new, }; static const struct nvkm_device_chip Loading @@ -990,7 +990,7 @@ nv94_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .cipher = g84_cipher_new, // .disp = g94_disp_new, // .dma = nv50_dma_new, Loading @@ -999,7 +999,7 @@ nv94_chipset = { // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, // .vp = g84_vp_new, .vp = g84_vp_new, }; static const struct nvkm_device_chip Loading @@ -1026,9 +1026,9 @@ nv96_chipset = { // .sw = nv50_sw_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .vp = g84_vp_new, .vp = g84_vp_new, // .cipher = g84_cipher_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .disp = g94_disp_new, // .pm = g84_pm_new, }; Loading Loading @@ -1083,7 +1083,7 @@ nva0_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .cipher = g84_cipher_new, // .disp = gt200_disp_new, // .dma = nv50_dma_new, Loading @@ -1092,7 +1092,7 @@ nva0_chipset = { // .mpeg = g84_mpeg_new, // .pm = gt200_pm_new, // .sw = nv50_sw_new, // .vp = g84_vp_new, .vp = g84_vp_new, }; static const struct nvkm_device_chip Loading Loading
drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h +1 −1 Original line number Diff line number Diff line #ifndef __NVKM_BSP_H__ #define __NVKM_BSP_H__ #include <engine/xtensa.h> extern struct nvkm_oclass g84_bsp_oclass; int g84_bsp_new(struct nvkm_device *, int, struct nvkm_engine **); #endif
drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h +1 −1 Original line number Diff line number Diff line #ifndef __NVKM_VP_H__ #define __NVKM_VP_H__ #include <engine/xtensa.h> extern struct nvkm_oclass g84_vp_oclass; int g84_vp_new(struct nvkm_device *, int, struct nvkm_engine **); #endif
drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h +8 −18 Original line number Diff line number Diff line Loading @@ -4,30 +4,20 @@ #include <core/engine.h> struct nvkm_xtensa { struct nvkm_engine engine; const struct nvkm_xtensa_func *func; u32 addr; struct nvkm_engine engine; struct nvkm_memory *gpu_fw; u32 fifo_val; u32 unkd28; }; int nvkm_xtensa_new_(const struct nvkm_xtensa_func *, struct nvkm_device *, int index, bool enable, u32 addr, struct nvkm_engine **); struct nvkm_xtensa_func { void (*init)(struct nvkm_xtensa *); u32 pmc_enable; u32 fifo_val; u32 unkd28; struct nvkm_sclass sclass[]; }; #define nvkm_xtensa_create(p,e,c,b,d,i,f,r) \ nvkm_xtensa_create_((p), (e), (c), (b), (d), (i), (f), \ sizeof(**r),(void **)r) int nvkm_xtensa_create_(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, u32, bool, const char *, const char *, int, void **); #define _nvkm_xtensa_dtor _nvkm_engine_dtor int _nvkm_xtensa_init(struct nvkm_object *); int _nvkm_xtensa_fini(struct nvkm_object *, bool); #endif
drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c +8 −30 Original line number Diff line number Diff line Loading @@ -26,41 +26,19 @@ #include <nvif/class.h> static const struct nvkm_xtensa_func g84_bsp_func = { g84_bsp = { .pmc_enable = 0x04008000, .fifo_val = 0x1111, .unkd28 = 0x90044, .sclass = { { -1, -1, NV74_BSP }, {} } }; static int g84_bsp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) int g84_bsp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { struct nvkm_xtensa *bsp; int ret; ret = nvkm_xtensa_create(parent, engine, oclass, 0x103000, true, "PBSP", "bsp", &bsp); *pobject = nv_object(bsp); if (ret) return ret; bsp->func = &g84_bsp_func; nv_subdev(bsp)->unit = 0x04008000; bsp->fifo_val = 0x1111; bsp->unkd28 = 0x90044; return 0; return nvkm_xtensa_new_(&g84_bsp, device, index, true, 0x103000, pengine); } struct nvkm_oclass g84_bsp_oclass = { .handle = NV_ENGINE(BSP, 0x84), .ofuncs = &(struct nvkm_ofuncs) { .ctor = g84_bsp_ctor, .dtor = _nvkm_xtensa_dtor, .init = _nvkm_xtensa_init, .fini = _nvkm_xtensa_fini, }, };
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +12 −12 Original line number Diff line number Diff line Loading @@ -897,7 +897,7 @@ nv84_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .cipher = g84_cipher_new, // .disp = g84_disp_new, // .dma = nv50_dma_new, Loading @@ -906,7 +906,7 @@ nv84_chipset = { // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, // .vp = g84_vp_new, .vp = g84_vp_new, }; static const struct nvkm_device_chip Loading @@ -928,7 +928,7 @@ nv86_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .cipher = g84_cipher_new, // .disp = g84_disp_new, // .dma = nv50_dma_new, Loading @@ -937,7 +937,7 @@ nv86_chipset = { // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, // .vp = g84_vp_new, .vp = g84_vp_new, }; static const struct nvkm_device_chip Loading @@ -959,7 +959,7 @@ nv92_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .cipher = g84_cipher_new, // .disp = g84_disp_new, // .dma = nv50_dma_new, Loading @@ -968,7 +968,7 @@ nv92_chipset = { // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, // .vp = g84_vp_new, .vp = g84_vp_new, }; static const struct nvkm_device_chip Loading @@ -990,7 +990,7 @@ nv94_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .cipher = g84_cipher_new, // .disp = g94_disp_new, // .dma = nv50_dma_new, Loading @@ -999,7 +999,7 @@ nv94_chipset = { // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, // .vp = g84_vp_new, .vp = g84_vp_new, }; static const struct nvkm_device_chip Loading @@ -1026,9 +1026,9 @@ nv96_chipset = { // .sw = nv50_sw_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .vp = g84_vp_new, .vp = g84_vp_new, // .cipher = g84_cipher_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .disp = g94_disp_new, // .pm = g84_pm_new, }; Loading Loading @@ -1083,7 +1083,7 @@ nva0_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, // .bsp = g84_bsp_new, .bsp = g84_bsp_new, // .cipher = g84_cipher_new, // .disp = gt200_disp_new, // .dma = nv50_dma_new, Loading @@ -1092,7 +1092,7 @@ nva0_chipset = { // .mpeg = g84_mpeg_new, // .pm = gt200_pm_new, // .sw = nv50_sw_new, // .vp = g84_vp_new, .vp = g84_vp_new, }; static const struct nvkm_device_chip Loading