Commit 98bae896 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx11: remove some register fields that no longer exist 



Some copy paste leftovers for older asics.  They were protected
by __BIG_ENDIAN, so we didn't notice them initially.

Reported-by: default avatarkernel test robot <lkp@intel.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d6ffefcc

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+0 −6
Original line number Diff line number Diff line
@@ -3409,9 +3409,6 @@ static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev) 
	rb_bufsz = order_base_2(ring->ring_size / 8);

	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

#ifdef __BIG_ENDIAN

	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);

#endif

	WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);



	/* Initialize the ring buffer's write pointers */
@@ -4059,9 +4056,6 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 
			    (order_base_2(prop->queue_size / 4) - 1));

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

			    ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));

#ifdef __BIG_ENDIAN

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

#endif

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+0 −3
Original line number Diff line number Diff line
@@ -693,9 +693,6 @@ static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 
			    (order_base_2(ring->ring_size / 4) - 1));

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

			    ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));

#ifdef __BIG_ENDIAN

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

#endif

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);