Commit 99bd5537 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nve6/gr: update initial register/context values 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent c4c7044f

drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c

+109 −108
Original line number Diff line number Diff line
@@ -749,6 +749,10 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv) 
	nv_icmd(priv, 0x000841, 0x08000080);

	nv_icmd(priv, 0x000842, 0x00400008);

	nv_icmd(priv, 0x000843, 0x08000080);

	switch (nv_device(priv)->chipset) {

	case 0xe6:

		break;

	default:

		nv_icmd(priv, 0x000818, 0x00000000);

		nv_icmd(priv, 0x000819, 0x00000000);

		nv_icmd(priv, 0x00081a, 0x00000000);
@@ -774,6 +778,8 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv) 
		nv_icmd(priv, 0x000856, 0x00000000);

		nv_icmd(priv, 0x000857, 0x00000000);

		nv_icmd(priv, 0x000738, 0x00000000);

		break;

	}

	nv_icmd(priv, 0x0006aa, 0x00000001);

	nv_icmd(priv, 0x0006ab, 0x00000002);

	nv_icmd(priv, 0x0006ac, 0x00000080);
@@ -862,6 +868,10 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv) 
	nv_icmd(priv, 0x000813, 0x00000006);

	nv_icmd(priv, 0x000814, 0x00000008);

	nv_icmd(priv, 0x000957, 0x00000003);

	switch (nv_device(priv)->chipset) {

	case 0xe6:

		break;

	default:

		nv_icmd(priv, 0x000818, 0x00000000);

		nv_icmd(priv, 0x000819, 0x00000000);

		nv_icmd(priv, 0x00081a, 0x00000000);
@@ -887,6 +897,8 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv) 
		nv_icmd(priv, 0x000856, 0x00000000);

		nv_icmd(priv, 0x000857, 0x00000000);

		nv_icmd(priv, 0x000738, 0x00000000);

		break;

	}

	nv_icmd(priv, 0x000b07, 0x00000002);

	nv_icmd(priv, 0x000b08, 0x00000100);

	nv_icmd(priv, 0x000b09, 0x00000100);
@@ -2162,7 +2174,14 @@ nve0_grctx_generate_902d(struct nvc0_graph_priv *priv) 
	nv_mthd(priv, 0x902d, 0x0244, 0x00000080);

	nv_mthd(priv, 0x902d, 0x0248, 0x00000100);

	nv_mthd(priv, 0x902d, 0x024c, 0x00000100);

	switch (nv_device(priv)->chipset) {

	case 0xe6:

		nv_mthd(priv, 0x902d, 0x3410, 0x80002006);

		break;

	default:

		nv_mthd(priv, 0x902d, 0x3410, 0x00000000);

		break;

	}

}



static void
@@ -2310,6 +2329,11 @@ nve0_graph_generate_unk58xx(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x405a00, 0x0);

	nv_wr32(priv, 0x405a04, 0x0);

	nv_wr32(priv, 0x405a18, 0x0);

}



static void

nve0_graph_generate_unk5bxx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x405b00, 0x0);

	nv_wr32(priv, 0x405b10, 0x1000);

}
@@ -2394,6 +2418,8 @@ nve0_graph_generate_unk88xx(struct nvc0_graph_priv *priv) 
static void

nve0_graph_generate_gpc(struct nvc0_graph_priv *priv)

{

	int i;



	nv_wr32(priv, 0x418380, 0x16);

	nv_wr32(priv, 0x418400, 0x38004e00);

	nv_wr32(priv, 0x418404, 0x71e0ffff);
@@ -2434,62 +2460,15 @@ nve0_graph_generate_gpc(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x418924, 0x0);

	nv_wr32(priv, 0x418928, 0xffff00);

	nv_wr32(priv, 0x41892c, 0xff00);

	nv_wr32(priv, 0x418a00, 0x0);

	nv_wr32(priv, 0x418a04, 0x0);

	nv_wr32(priv, 0x418a08, 0x0);

	nv_wr32(priv, 0x418a0c, 0x10000);

	nv_wr32(priv, 0x418a10, 0x0);

	nv_wr32(priv, 0x418a14, 0x0);

	nv_wr32(priv, 0x418a18, 0x0);

	nv_wr32(priv, 0x418a20, 0x0);

	nv_wr32(priv, 0x418a24, 0x0);

	nv_wr32(priv, 0x418a28, 0x0);

	nv_wr32(priv, 0x418a2c, 0x10000);

	nv_wr32(priv, 0x418a30, 0x0);

	nv_wr32(priv, 0x418a34, 0x0);

	nv_wr32(priv, 0x418a38, 0x0);

	nv_wr32(priv, 0x418a40, 0x0);

	nv_wr32(priv, 0x418a44, 0x0);

	nv_wr32(priv, 0x418a48, 0x0);

	nv_wr32(priv, 0x418a4c, 0x10000);

	nv_wr32(priv, 0x418a50, 0x0);

	nv_wr32(priv, 0x418a54, 0x0);

	nv_wr32(priv, 0x418a58, 0x0);

	nv_wr32(priv, 0x418a60, 0x0);

	nv_wr32(priv, 0x418a64, 0x0);

	nv_wr32(priv, 0x418a68, 0x0);

	nv_wr32(priv, 0x418a6c, 0x10000);

	nv_wr32(priv, 0x418a70, 0x0);

	nv_wr32(priv, 0x418a74, 0x0);

	nv_wr32(priv, 0x418a78, 0x0);

	nv_wr32(priv, 0x418a80, 0x0);

	nv_wr32(priv, 0x418a84, 0x0);

	nv_wr32(priv, 0x418a88, 0x0);

	nv_wr32(priv, 0x418a8c, 0x10000);

	nv_wr32(priv, 0x418a90, 0x0);

	nv_wr32(priv, 0x418a94, 0x0);

	nv_wr32(priv, 0x418a98, 0x0);

	nv_wr32(priv, 0x418aa0, 0x0);

	nv_wr32(priv, 0x418aa4, 0x0);

	nv_wr32(priv, 0x418aa8, 0x0);

	nv_wr32(priv, 0x418aac, 0x10000);

	nv_wr32(priv, 0x418ab0, 0x0);

	nv_wr32(priv, 0x418ab4, 0x0);

	nv_wr32(priv, 0x418ab8, 0x0);

	nv_wr32(priv, 0x418ac0, 0x0);

	nv_wr32(priv, 0x418ac4, 0x0);

	nv_wr32(priv, 0x418ac8, 0x0);

	nv_wr32(priv, 0x418acc, 0x10000);

	nv_wr32(priv, 0x418ad0, 0x0);

	nv_wr32(priv, 0x418ad4, 0x0);

	nv_wr32(priv, 0x418ad8, 0x0);

	nv_wr32(priv, 0x418ae0, 0x0);

	nv_wr32(priv, 0x418ae4, 0x0);

	nv_wr32(priv, 0x418ae8, 0x0);

	nv_wr32(priv, 0x418aec, 0x10000);

	nv_wr32(priv, 0x418af0, 0x0);

	nv_wr32(priv, 0x418af4, 0x0);

	nv_wr32(priv, 0x418af8, 0x0);

	for (i = 0; i < 8; i++) {

		nv_wr32(priv, 0x418a00 + (i * 0x20), 0x0);

		nv_wr32(priv, 0x418a04 + (i * 0x20), 0x0);

		nv_wr32(priv, 0x418a08 + (i * 0x20), 0x0);

		nv_wr32(priv, 0x418a0c + (i * 0x20), 0x10000);

		nv_wr32(priv, 0x418a10 + (i * 0x20), 0x0);

		nv_wr32(priv, 0x418a14 + (i * 0x20), 0x0);

		nv_wr32(priv, 0x418a18 + (i * 0x20), 0x0);

	}

	nv_wr32(priv, 0x418b00, 0x6);

	nv_wr32(priv, 0x418b08, 0xa418820);

	nv_wr32(priv, 0x418b0c, 0x62080e6);
@@ -2567,7 +2546,14 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x419e90, 0x0);

	nv_wr32(priv, 0x419e94, 0x0);

	nv_wr32(priv, 0x419e98, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xe6:

		nv_wr32(priv, 0x419eac, 0x1f8f);

		break;

	default:

		nv_wr32(priv, 0x419eac, 0x1fcf);

		break;

	}

	nv_wr32(priv, 0x419eb0, 0xd3f);

	nv_wr32(priv, 0x419ec8, 0x1304f);

	nv_wr32(priv, 0x419f30, 0x0);
@@ -2579,7 +2565,21 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x419f48, 0x0);

	nv_wr32(priv, 0x419f4c, 0x0);

	nv_wr32(priv, 0x419f58, 0x0);

	switch (nv_device(priv)->chipset) {

	case 0xe6:

		nv_wr32(priv, 0x419f70, 0x0);

		break;

	default:

		break;

	}

	nv_wr32(priv, 0x419f78, 0xb);

	switch (nv_device(priv)->chipset) {

	case 0xe6:

		nv_wr32(priv, 0x419f7c, 0x27a);

		break;

	default:

		break;

	}

}



static void
@@ -2624,6 +2624,7 @@ nve0_grctx_generate(struct nvc0_graph_priv *priv) 
	nve0_graph_generate_unk46xx(priv);

	nve0_graph_generate_unk47xx(priv);

	nve0_graph_generate_unk58xx(priv);

	nve0_graph_generate_unk5bxx(priv);

	nve0_graph_generate_unk60xx(priv);

	nve0_graph_generate_unk64xx(priv);

	nve0_graph_generate_unk70xx(priv);

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc

+24 −2
Original line number Diff line number Diff line
@@ -60,8 +60,8 @@ chipsets: 
.b8  0xe6 0 0 0

.b16 #nve4_gpc_mmio_head

.b16 #nve4_gpc_mmio_tail

.b16 #nve4_tpc_mmio_head

.b16 #nve4_tpc_mmio_tail

.b16 #nve6_tpc_mmio_head

.b16 #nve6_tpc_mmio_tail

.b8  0 0 0 0



// GPC mmio lists
@@ -123,6 +123,28 @@ mmctx_data(0x000758, 1) 
mmctx_data(0x000778, 1)

nve4_tpc_mmio_tail:



nve6_tpc_mmio_head:

mmctx_data(0x000048, 1)

mmctx_data(0x000064, 1)

mmctx_data(0x000088, 1)

mmctx_data(0x000200, 6)

mmctx_data(0x00021c, 2)

mmctx_data(0x000230, 1)

mmctx_data(0x0002c4, 1)

mmctx_data(0x000400, 3)

mmctx_data(0x000420, 3)

mmctx_data(0x0004e8, 1)

mmctx_data(0x0004f4, 1)

mmctx_data(0x000604, 4)

mmctx_data(0x000644, 22)

mmctx_data(0x0006ac, 2)

mmctx_data(0x0006c8, 1)

mmctx_data(0x000730, 8)

mmctx_data(0x000758, 1)

mmctx_data(0x000770, 1)

mmctx_data(0x000778, 2)

nve6_tpc_mmio_tail:



.section #nve0_grgpc_code

bra #init

define(`include_code')

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h

+22 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ uint32_t nve0_grgpc_data[] = { 
	0x01580110,

	0x000000e6,

	0x0110008c,

	0x01580110,

	0x01a40158,

	0x00000000,

/* 0x008c: nve4_gpc_mmio_head */

	0x00000380,
@@ -97,6 +97,27 @@ uint32_t nve0_grgpc_data[] = { 
	0x1c000730,

	0x00000758,

	0x00000778,

/* 0x0158: nve4_tpc_mmio_tail */

/* 0x0158: nve6_tpc_mmio_head */

	0x00000048,

	0x00000064,

	0x00000088,

	0x14000200,

	0x0400021c,

	0x00000230,

	0x000002c4,

	0x08000400,

	0x08000420,

	0x000004e8,

	0x000004f4,

	0x0c000604,

	0x54000644,

	0x040006ac,

	0x000006c8,

	0x1c000730,

	0x00000758,

	0x00000770,

	0x04000778,

};



uint32_t nve0_grgpc_code[] = {

drivers/gpu/drm/nouveau/core/engine/graph/nve0.c

+228 −2
Original line number Diff line number Diff line
@@ -512,19 +512,224 @@ nve0_graph_init_regs(struct nvc0_graph_priv *priv) 
	nv_wr32(priv, 0x400124, 0x00000002);

}



static void

nve0_graph_init_unk40xx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x40415c, 0x00000000);

	nv_wr32(priv, 0x404170, 0x00000000);

}



static void

nve0_graph_init_unk44xx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x404488, 0x00000000);

	nv_wr32(priv, 0x40448c, 0x00000000);

}



static void

nve0_graph_init_unk78xx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x407808, 0x00000000);

}



static void

nve0_graph_init_unk60xx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x406024, 0x00000000);

}



static void

nve0_graph_init_unk64xx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x4064f0, 0x00000000);

	nv_wr32(priv, 0x4064f4, 0x00000000);

	nv_wr32(priv, 0x4064f8, 0x00000000);

}



static void

nve0_graph_init_unk58xx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x405844, 0x00ffffff);

	nv_wr32(priv, 0x405850, 0x00000000);

	nv_wr32(priv, 0x405900, 0x0000ff34);

	nv_wr32(priv, 0x405908, 0x00000000);

	nv_wr32(priv, 0x405928, 0x00000000);

	nv_wr32(priv, 0x40592c, 0x00000000);

}



static void

nve0_graph_init_unk80xx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x40803c, 0x00000000);

}



static void

nve0_graph_init_unk70xx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x407010, 0x00000000);

}



static void

nve0_graph_init_unk5bxx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x405b50, 0x00000000);

}



static void

nve0_graph_init_gpc(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x418408, 0x00000000);

	nv_wr32(priv, 0x4184a0, 0x00000000);

	nv_wr32(priv, 0x4184a4, 0x00000000);

	nv_wr32(priv, 0x4184a8, 0x00000000);

	nv_wr32(priv, 0x418604, 0x00000000);

	nv_wr32(priv, 0x418680, 0x00000000);

	nv_wr32(priv, 0x418714, 0x00000000);

	nv_wr32(priv, 0x418384, 0x00000000);

	nv_wr32(priv, 0x418814, 0x00000000);

	nv_wr32(priv, 0x418818, 0x00000000);

	nv_wr32(priv, 0x41881c, 0x00000000);

	nv_wr32(priv, 0x418b04, 0x00000000);

	nv_wr32(priv, 0x4188c8, 0x00000000);

	nv_wr32(priv, 0x4188cc, 0x00000000);

	nv_wr32(priv, 0x4188d0, 0x00010000);

	nv_wr32(priv, 0x4188d4, 0x00000001);

	nv_wr32(priv, 0x418910, 0x00010001);

	nv_wr32(priv, 0x418914, 0x00000301);

	nv_wr32(priv, 0x418918, 0x00800000);

	nv_wr32(priv, 0x418980, 0x77777770);

	nv_wr32(priv, 0x418984, 0x77777777);

	nv_wr32(priv, 0x418988, 0x77777777);

	nv_wr32(priv, 0x41898c, 0x77777777);

	nv_wr32(priv, 0x418c04, 0x00000000);

	nv_wr32(priv, 0x418c64, 0x00000000);

	nv_wr32(priv, 0x418c68, 0x00000000);

	nv_wr32(priv, 0x418c88, 0x00000000);

	nv_wr32(priv, 0x418cb4, 0x00000000);

	nv_wr32(priv, 0x418cb8, 0x00000000);

	nv_wr32(priv, 0x418d00, 0x00000000);

	nv_wr32(priv, 0x418d28, 0x00000000);

	nv_wr32(priv, 0x418d2c, 0x00000000);

	nv_wr32(priv, 0x418f00, 0x00000000);

	nv_wr32(priv, 0x418f08, 0x00000000);

	nv_wr32(priv, 0x418f20, 0x00000000);

	nv_wr32(priv, 0x418f24, 0x00000000);

	nv_wr32(priv, 0x418e00, 0x00000060);

	nv_wr32(priv, 0x418e08, 0x00000000);

	nv_wr32(priv, 0x418e1c, 0x00000000);

	nv_wr32(priv, 0x418e20, 0x00000000);

	nv_wr32(priv, 0x41900c, 0x00000000);

	nv_wr32(priv, 0x419018, 0x00000000);

}



static void

nve0_graph_init_tpc(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x419d0c, 0x00000000);

	nv_wr32(priv, 0x419d10, 0x00000014);

	nv_wr32(priv, 0x419ab0, 0x00000000);

	nv_wr32(priv, 0x419ac8, 0x00000000);

	nv_wr32(priv, 0x419ab8, 0x000000e7);

	nv_wr32(priv, 0x419abc, 0x00000000);

	nv_wr32(priv, 0x419ac0, 0x00000000);

	nv_wr32(priv, 0x419ab4, 0x00000000);

	nv_wr32(priv, 0x41980c, 0x00000010);

	nv_wr32(priv, 0x419844, 0x00000000);

	nv_wr32(priv, 0x419850, 0x00000004);

	nv_wr32(priv, 0x419854, 0x00000000);

	nv_wr32(priv, 0x419858, 0x00000000);

	nv_wr32(priv, 0x419c98, 0x00000000);

	nv_wr32(priv, 0x419ca8, 0x00000000);

	nv_wr32(priv, 0x419cb0, 0x01000000);

	nv_wr32(priv, 0x419cb4, 0x00000000);

	nv_wr32(priv, 0x419cb8, 0x00b08bea);

	nv_wr32(priv, 0x419c84, 0x00010384);

	nv_wr32(priv, 0x419cbc, 0x28137646);

	nv_wr32(priv, 0x419cc0, 0x00000000);

	nv_wr32(priv, 0x419cc4, 0x00000000);

	nv_wr32(priv, 0x419c80, 0x00020232);

	nv_wr32(priv, 0x419c0c, 0x00000000);

	nv_wr32(priv, 0x419e00, 0x00000000);

	nv_wr32(priv, 0x419ea0, 0x00000000);

	nv_wr32(priv, 0x419ee4, 0x00000000);

	nv_wr32(priv, 0x419ea4, 0x00000100);

	nv_wr32(priv, 0x419ea8, 0x00000000);

	nv_wr32(priv, 0x419eb4, 0x00000000);

	nv_wr32(priv, 0x419eb8, 0x00000000);

	nv_wr32(priv, 0x419ebc, 0x00000000);

	nv_wr32(priv, 0x419ec0, 0x00000000);

	nv_wr32(priv, 0x419edc, 0x00000000);

	nv_wr32(priv, 0x419f00, 0x00000000);

	nv_wr32(priv, 0x419f74, 0x00000555);

}



static void

nve0_graph_init_tpcunk(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x41be04, 0x00000000);

	nv_wr32(priv, 0x41be08, 0x00000004);

	nv_wr32(priv, 0x41be0c, 0x00000000);

	nv_wr32(priv, 0x41be10, 0x003b8bc7);

	nv_wr32(priv, 0x41be14, 0x00000000);

	nv_wr32(priv, 0x41be18, 0x00000000);

	nv_wr32(priv, 0x41bfd4, 0x00800000);

	nv_wr32(priv, 0x41bfdc, 0x00000000);

	nv_wr32(priv, 0x41bff8, 0x00000000);

	nv_wr32(priv, 0x41bffc, 0x00000000);

	nv_wr32(priv, 0x41becc, 0x00000000);

	nv_wr32(priv, 0x41bee8, 0x00000000);

	nv_wr32(priv, 0x41beec, 0x00000000);

}



static void

nve0_graph_init_unk88xx(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x40880c, 0x00000000);

	nv_wr32(priv, 0x408850, 0x00000004);

	nv_wr32(priv, 0x408910, 0x00000000);

	nv_wr32(priv, 0x408914, 0x00000000);

	nv_wr32(priv, 0x408918, 0x00000000);

	nv_wr32(priv, 0x40891c, 0x00000000);

	nv_wr32(priv, 0x408920, 0x00000000);

	nv_wr32(priv, 0x408924, 0x00000000);

	nv_wr32(priv, 0x408928, 0x00000000);

	nv_wr32(priv, 0x40892c, 0x00000000);

	nv_wr32(priv, 0x408930, 0x00000000);

	nv_wr32(priv, 0x408950, 0x00000000);

	nv_wr32(priv, 0x408954, 0x0000ffff);

	nv_wr32(priv, 0x408958, 0x00000034);

	nv_wr32(priv, 0x408984, 0x00000000);

	nv_wr32(priv, 0x408988, 0x08040201);

	nv_wr32(priv, 0x40898c, 0x80402010);

}



static void

nve0_graph_init_units(struct nvc0_graph_priv *priv)

{

	nv_wr32(priv, 0x409ffc, 0x00000000);

	nv_wr32(priv, 0x409c14, 0x00003e3e);

	switch (nv_device(priv)->chipset) {

	case 0xe6:

		nv_wr32(priv, 0x409c24, 0x000f0001);

		break;

	default:

		nv_wr32(priv, 0x409c24, 0x000f0000);

		break;

	}



	nv_wr32(priv, 0x404000, 0xc0000000);

	nv_wr32(priv, 0x404600, 0xc0000000);

	nv_wr32(priv, 0x408030, 0xc0000000);

	nv_wr32(priv, 0x404490, 0xc0000000);

	nv_wr32(priv, 0x406018, 0xc0000000);

	switch (nv_device(priv)->chipset) {

	case 0xe6:

		nv_wr32(priv, 0x407020, 0x40000000);

		break;

	default:

		nv_wr32(priv, 0x407020, 0xc0000000);

		break;

	}

	nv_wr32(priv, 0x405840, 0xc0000000);

	nv_wr32(priv, 0x405844, 0x00ffffff);
@@ -760,6 +965,27 @@ nve0_graph_init(struct nouveau_object *object) 


	nve0_graph_init_obj418880(priv);

	nve0_graph_init_regs(priv);



	switch (nv_device(priv)->chipset) {

	case 0xe6:

		nve0_graph_init_unk40xx(priv);

		nve0_graph_init_unk44xx(priv);

		nve0_graph_init_unk78xx(priv);

		nve0_graph_init_unk60xx(priv);

		nve0_graph_init_unk64xx(priv);

		nve0_graph_init_unk58xx(priv);

		nve0_graph_init_unk80xx(priv);

		nve0_graph_init_unk70xx(priv);

		nve0_graph_init_unk5bxx(priv);

		nve0_graph_init_gpc(priv);

		nve0_graph_init_tpc(priv);

		nve0_graph_init_tpcunk(priv);

		nve0_graph_init_unk88xx(priv);

		break;

	default:

		break;

	}



	nve0_graph_init_gpc_0(priv);



	nv_wr32(priv, 0x400500, 0x00010001);