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Commit 9b8777e3 authored by John Crispin's avatar John Crispin Committed by Greg Kroah-Hartman
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serial: of: add a PORT_RT2880 definition



The Ralink RT2880 SoC and its successors have an internal 8250 core. This core
needs the same quirks applied as the AMD AU1xxx uart. In addition to these
quirks, the ports memory region is only 0x100 unlike the AU1xxx which has a
size of 0x1000.

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 7af0ea5d
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