Commit 9cb9480e authored by Jan Glauber's avatar Jan Glauber Committed by Wolfram Sang
Browse files

i2c: octeon: Rename [read|write]_sw to reg_[read|write] 



Rename the [read|write]_sw functions to make it clearer they access
the TWSI registers.

Signed-off-by: default avatarJan Glauber <jglauber@cavium.com>
Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
parent f541bb38

drivers/i2c/busses/i2c-octeon.c

+26 −26
Original line number Original line Diff line number Diff line
@@ -80,14 +80,14 @@ struct octeon_i2c { 
};

};





/**

/**

 * octeon_i2c_write_sw - write an I2C core register

 * octeon_i2c_reg_write - write an I2C core register

 * @i2c: The struct octeon_i2c

 * @i2c: The struct octeon_i2c

 * @eop_reg: Register selector

 * @eop_reg: Register selector

 * @data: Value to be written

 * @data: Value to be written

 *

 *

 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.

 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.

 */

 */

static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)

static void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)

{

{

	u64 tmp;

	u64 tmp;
@@ -98,7 +98,7 @@ static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data) 
}

}





/**

/**

 * octeon_i2c_read_sw - read lower bits of an I2C core register

 * octeon_i2c_reg_read - read lower bits of an I2C core register

 * @i2c: The struct octeon_i2c

 * @i2c: The struct octeon_i2c

 * @eop_reg: Register selector

 * @eop_reg: Register selector

 *

 *
@@ -106,7 +106,7 @@ static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data) 
 *

 *

 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.

 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.

 */

 */

static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)

static u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)

{

{

	u64 tmp;

	u64 tmp;
@@ -189,7 +189,7 @@ static irqreturn_t octeon_i2c_isr(int irq, void *dev_id) 




static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)

static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)

{

{

	return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;

	return (octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;

}

}





/**

/**
@@ -252,8 +252,8 @@ static void octeon_i2c_set_clock(struct octeon_i2c *i2c) 
			}

			}

		}

		}

	}

	}

	octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);

	octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);

	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);

}

}





static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)

static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
@@ -262,14 +262,14 @@ static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c) 
	int tries;

	int tries;





	/* disable high level controller, enable bus access */

	/* disable high level controller, enable bus access */

	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);





	/* reset controller */

	/* reset controller */

	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);





	for (tries = 10; tries; tries--) {

	for (tries = 10; tries; tries--) {

		udelay(1);

		udelay(1);

		status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);

		status = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);

		if (status == STAT_IDLE)

		if (status == STAT_IDLE)

			return 0;

			return 0;

	}

	}
@@ -288,19 +288,19 @@ static int octeon_i2c_start(struct octeon_i2c *i2c) 
	int result;

	int result;

	u8 data;

	u8 data;





	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,

			    TWSI_CTL_ENAB | TWSI_CTL_STA);

			    TWSI_CTL_ENAB | TWSI_CTL_STA);





	result = octeon_i2c_wait(i2c);

	result = octeon_i2c_wait(i2c);

	if (result) {

	if (result) {

		if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {

		if (octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {

			/*

			/*

			 * Controller refused to send start flag May

			 * Controller refused to send start flag May

			 * be a client is holding SDA low - let's try

			 * be a client is holding SDA low - let's try

			 * to free it.

			 * to free it.

			 */

			 */

			octeon_i2c_unblock(i2c);

			octeon_i2c_unblock(i2c);

			octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,

			octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,

					    TWSI_CTL_ENAB | TWSI_CTL_STA);

					    TWSI_CTL_ENAB | TWSI_CTL_STA);

			result = octeon_i2c_wait(i2c);

			result = octeon_i2c_wait(i2c);

		}

		}
@@ -308,7 +308,7 @@ static int octeon_i2c_start(struct octeon_i2c *i2c) 
			return result;

			return result;

	}

	}





	data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);

	data = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);

	if ((data != STAT_START) && (data != STAT_RSTART)) {

	if ((data != STAT_START) && (data != STAT_RSTART)) {

		dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);

		dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);

		return -EIO;

		return -EIO;
@@ -320,7 +320,7 @@ static int octeon_i2c_start(struct octeon_i2c *i2c) 
/* send STOP to the bus */

/* send STOP to the bus */

static void octeon_i2c_stop(struct octeon_i2c *i2c)

static void octeon_i2c_stop(struct octeon_i2c *i2c)

{

{

	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,

			    TWSI_CTL_ENAB | TWSI_CTL_STP);

			    TWSI_CTL_ENAB | TWSI_CTL_STP);

}

}
@@ -345,15 +345,15 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target, 
	if (result)

	if (result)

		return result;

		return result;





	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);

	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);





	result = octeon_i2c_wait(i2c);

	result = octeon_i2c_wait(i2c);

	if (result)

	if (result)

		return result;

		return result;





	for (i = 0; i < length; i++) {

	for (i = 0; i < length; i++) {

		tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);

		tmp = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);





		if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {

		if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {

			dev_err(i2c->dev,

			dev_err(i2c->dev,
@@ -362,8 +362,8 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target, 
			return -EIO;

			return -EIO;

		}

		}





		octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);

		octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);

		octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

		octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);





		result = octeon_i2c_wait(i2c);

		result = octeon_i2c_wait(i2c);

		if (result)

		if (result)
@@ -398,15 +398,15 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, 
	if (result)

	if (result)

		return result;

		return result;





	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);

	octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);

	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);





	result = octeon_i2c_wait(i2c);

	result = octeon_i2c_wait(i2c);

	if (result)

	if (result)

		return result;

		return result;





	for (i = 0; i < length; i++) {

	for (i = 0; i < length; i++) {

		tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);

		tmp = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT);





		if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {

		if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {

			dev_err(i2c->dev,

			dev_err(i2c->dev,
@@ -416,17 +416,17 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, 
		}

		}





		if (i + 1 < length)

		if (i + 1 < length)

			octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,

			octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,

					    TWSI_CTL_ENAB | TWSI_CTL_AAK);

					    TWSI_CTL_ENAB | TWSI_CTL_AAK);

		else

		else

			octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,

			octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL,

					    TWSI_CTL_ENAB);

					    TWSI_CTL_ENAB);





		result = octeon_i2c_wait(i2c);

		result = octeon_i2c_wait(i2c);

		if (result)

		if (result)

			return result;

			return result;





		data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);

		data[i] = octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA);

		if (recv_len && i == 0) {

		if (recv_len && i == 0) {

			if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {

			if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {

				dev_err(i2c->dev,

				dev_err(i2c->dev,