Unverified Commit 9cc2df42 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v6.0-next-dts64' of... 

Merge tag 'v6.0-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt6795:
- add add system timer node

mt7986a:
- add wifi support

mt8183:
- add MDP3 and keypad

mt8186:
- basic support for the Evaluation Board including, i2c, usb and uart.

mt8192:
- add nodes to support PWM, MIPI transciever, display with GCE and DSI.

mt8195:
- disable nodes not used on all boards
- Add support for CPU freq, clocks, power domain controller, spmi, scp.
- Enable audio decoder, DSP, IOMMU, mailbox.
- Add display nodes for vdosys0.
- On Cherry based chromebooks, enable the system companion processor,
  Cross EC, Google Security Chip, secondary MMC controller, trackpad and
  a few regulators.

* tag 'v6.0-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (34 commits)
  arm64: dts: mediatek: mt6795: Add CPUX system timer node
  arm64: dts: mt7986: add built-in Wi-Fi device nodes
  arm64: dts: mediatek: cherry: Enable MT6315 regulators on SPMI bus
  arm64: dts: mediatek: cherry: Enable Elantech eKTH3000 i2c trackpad
  arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller
  arm64: dts: mediatek: cherry: Add keyboard mapping for the top row
  arm64: dts: mediatek: cherry: Add Google Security Chip (GSC) TPM
  arm64: dts: mediatek: cherry: Wire up the ChromeOS Embedded Controller
  arm64: dts: mediatek: cherry: Enable the System Companion Processor
  arm64: dts: mediatek: Fix build warnings of mt8173 vcodec nodes
  arm64: dts: mediatek: Add missing xHCI clocks for mt8192 and mt8195
  arm64: dts: mt8192: Add dsi node
  arm64: dts: mt8192: Add display nodes
  arm64: dts: mediatek: Add mmsys #reset-cells property for mt8192
  arm64: dts: mt8192: Add mipi_tx node
  arm64: dts: mt8192: Add pwm node
  arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile
  arm64: dts: mt8195: Add display node for vdosys0
  arm64: dts: mt8195: Add gce node
  arm64: dts: mt8195: Add iommu and smi nodes
  ...

Link: https://lore.kernel.org/r/3b915692-c8a9-c508-5a4a-0fdb49355e99@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9d88bf08 5ebb14aa

arch/arm64/boot/dts/mediatek/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb 
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb

arch/arm64/boot/dts/mediatek/mt6795.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -230,6 +230,14 @@ sysirq: intpol-controller@10200620 { 
			reg = <0 0x10200620 0 0x20>;

		};



		systimer: timer@10200670 {

			compatible = "mediatek,mt6795-systimer";

			reg = <0 0x10200670 0 0x10>;

			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&system_clk>;

			clock-names = "clk13m";

		};



		gic: interrupt-controller@10221000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;

arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts

+38 −0
Original line number Diff line number Diff line
@@ -115,6 +115,13 @@ &uart2 { 
	status = "okay";

};



&wifi {

	status = "okay";

	pinctrl-names = "default", "dbdc";

	pinctrl-0 = <&wf_2g_5g_pins>;

	pinctrl-1 = <&wf_dbdc_pins>;

};



&pio {

	uart1_pins: uart1-pins {

		mux {
@@ -129,4 +136,35 @@ mux { 
			groups = "uart2";

		};

	};



	wf_2g_5g_pins: wf-2g-5g-pins {

		mux {

			function = "wifi";

			groups = "wf_2g", "wf_5g";

		};

		conf {

			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",

			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",

			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",

			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",

			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",

			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",

			       "WF1_TOP_CLK", "WF1_TOP_DATA";

			drive-strength = <4>;

		};

	};



	wf_dbdc_pins: wf-dbdc-pins {

		mux {

			function = "wifi";

			groups = "wf_dbdc";

		};

		conf {

			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",

			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",

			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",

			       "WF0_TOP_CLK", "WF0_TOP_DATA";

			drive-strength = <4>;

		};

	};

};

arch/arm64/boot/dts/mediatek/mt7986a.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/mt7986-clk.h>

#include <dt-bindings/reset/mt7986-resets.h>



/ {

	interrupt-parent = <&gic>;
@@ -70,6 +71,11 @@ secmon_reserved: secmon@43000000 { 
			reg = <0 0x43000000 0 0x30000>;

			no-map;

		};



		wmcpu_emi: wmcpu-reserved@4fc00000 {

			no-map;

			reg = <0 0x4fc00000 0 0x00100000>;

		};

	};



	timer {
@@ -261,6 +267,23 @@ eth: ethernet@15100000 { 
			#size-cells = <0>;

			status = "disabled";

		};



		wifi: wifi@18000000 {

			compatible = "mediatek,mt7986-wmac";

			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;

			reset-names = "consys";

			clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,

				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;

			clock-names = "mcu", "ap2conn";

			reg = <0 0x18000000 0 0x1000000>,

			      <0 0x10003000 0 0x1000>,

			      <0 0x11d10000 0 0x1000>;

			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;

			memory-region = <&wmcpu_emi>;

		};

	};



};

arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts

+40 −0
Original line number Diff line number Diff line
@@ -98,3 +98,43 @@ fixed-link { 
		};

	};

};



&wifi {

	status = "okay";

	pinctrl-names = "default", "dbdc";

	pinctrl-0 = <&wf_2g_5g_pins>;

	pinctrl-1 = <&wf_dbdc_pins>;

};



&pio {

	wf_2g_5g_pins: wf-2g-5g-pins {

		mux {

			function = "wifi";

			groups = "wf_2g", "wf_5g";

		};

		conf {

			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",

			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",

			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",

			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",

			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",

			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",

			       "WF1_TOP_CLK", "WF1_TOP_DATA";

			drive-strength = <4>;

		};

	};



	wf_dbdc_pins: wf-dbdc-pins {

		mux {

			function = "wifi";

			groups = "wf_dbdc";

		};

		conf {

			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",

			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",

			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",

			       "WF0_TOP_CLK", "WF0_TOP_DATA";

			drive-strength = <4>;

		};

	};

};