Commit 9d3f2e7e authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r8a77980: condor/v3hsk: Add QSPI flash support 



Define the Condor/V3HSK board dependent parts of the RPC-IF device node.
Add device nodes for Spansion S25FS512S SPI flash and MTD partitions on it.

Based on the original patches by Dmitry Shifrin.

Signed-off-by: default avatarDmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/322ca212-a45f-cd2c-f1eb-737f0aa42d22@cogentembedded.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 3b674382

arch/arm64/boot/dts/renesas/r8a77980-condor.dts

+67 −0
Original line number Diff line number Diff line
@@ -262,6 +262,11 @@ mmc_pins_uhs: mmc_uhs { 
		power-source = <1800>;

	};



	qspi0_pins: qspi0 {

		groups = "qspi0_ctrl", "qspi0_data4";

		function = "qspi0";

	};



	scif0_pins: scif0 {

		groups = "scif0_data";

		function = "scif0";
@@ -273,6 +278,68 @@ scif_clk_pins: scif_clk { 
	};

};



&rpc {

	pinctrl-0 = <&qspi0_pins>;

	pinctrl-names = "default";



	status = "okay";



	flash@0 {

		compatible = "spansion,s25fs512s", "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <50000000>;

		spi-rx-bus-width = <4>;



		partitions {

			compatible = "fixed-partitions";

			#address-cells = <1>;

			#size-cells = <1>;



			bootparam@0 {

				reg = <0x00000000 0x040000>;

				read-only;

			};

			cr7@40000 {

				reg = <0x00040000 0x080000>;

				read-only;

			};

			cert_header_sa3@c0000 {

				reg = <0x000c0000 0x080000>;

				read-only;

			};

			bl2@140000 {

				reg = <0x00140000 0x040000>;

				read-only;

			};

			cert_header_sa6@180000 {

				reg = <0x00180000 0x040000>;

				read-only;

			};

			bl31@1c0000 {

				reg = <0x001c0000 0x460000>;

				read-only;

			};

			uboot@640000 {

				reg = <0x00640000 0x0c0000>;

				read-only;

			};

			uboot-env@700000 {

				reg = <0x00700000 0x040000>;

				read-only;

			};

			dtb@740000 {

				reg = <0x00740000 0x080000>;

			};

			kernel@7c0000 {

				reg = <0x007c0000 0x1400000>;

			};

			user@1bc0000 {

				reg = <0x01bc0000 0x2440000>;

			};

		};

	};

};



&rwdt {

	timeout-sec = <60>;

	status = "okay";

arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts

+67 −0
Original line number Diff line number Diff line
@@ -187,6 +187,11 @@ i2c0_pins: i2c0 { 
		function = "i2c0";

	};



	qspi0_pins: qspi0 {

		groups = "qspi0_ctrl", "qspi0_data4";

		function = "qspi0";

	};



	scif0_pins: scif0 {

		groups = "scif0_data";

		function = "scif0";
@@ -198,6 +203,68 @@ scif_clk_pins: scif_clk { 
	};

};



&rpc {

	pinctrl-0 = <&qspi0_pins>;

	pinctrl-names = "default";



	status = "okay";



	flash@0 {

		compatible = "spansion,s25fs512s", "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <50000000>;

		spi-rx-bus-width = <4>;



		partitions {

			compatible = "fixed-partitions";

			#address-cells = <1>;

			#size-cells = <1>;



			bootparam@0 {

				reg = <0x00000000 0x040000>;

				read-only;

			};

			cr7@40000 {

				reg = <0x00040000 0x080000>;

				read-only;

			};

			cert_header_sa3@c0000 {

				reg = <0x000c0000 0x080000>;

				read-only;

			};

			bl2@140000 {

				reg = <0x00140000 0x040000>;

				read-only;

			};

			cert_header_sa6@180000 {

				reg = <0x00180000 0x040000>;

				read-only;

			};

			bl31@1c0000 {

				reg = <0x001c0000 0x460000>;

				read-only;

			};

			uboot@640000 {

				reg = <0x00640000 0x0c0000>;

				read-only;

			};

			uboot-env@700000 {

				reg = <0x00700000 0x040000>;

				read-only;

			};

			dtb@740000 {

				reg = <0x00740000 0x080000>;

			};

			kernel@7c0000 {

				reg = <0x007c0000 0x1400000>;

			};

			user@1bc0000 {

				reg = <0x01bc0000 0x2440000>;

			};

		};

	};

};



&rwdt {

	timeout-sec = <60>;

	status = "okay";