Loading arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +2 −0 Original line number Diff line number Diff line Loading @@ -40,6 +40,8 @@ /* SIC Registers */ #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) Loading arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +1 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ /* SIC Registers */ #define SIC_RVECT 0xffc00108 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ Loading Loading
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +2 −0 Original line number Diff line number Diff line Loading @@ -40,6 +40,8 @@ /* SIC Registers */ #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) Loading
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +1 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ /* SIC Registers */ #define SIC_RVECT 0xffc00108 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ Loading