Commit 9ef42640 authored by Kathiravan T's avatar Kathiravan T Committed by Bjorn Andersson
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arm64: dts: qcom: ipq9574: add few device nodes 



Add QUP(SPI / I2C) peripheral, PRNG, WDOG and the remaining UART nodes.
While at it, enable the SPI NOR in RDP433 board.

Signed-off-by: default avatarKathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517072806.13170-1-quic_kathirav@quicinc.com
parent fdb0038e

arch/arm64/boot/dts/qcom/ipq9574.dtsi

+202 −0
Original line number Diff line number Diff line
@@ -116,6 +116,13 @@ soc: soc@0 { 
		#size-cells = <1>;

		ranges = <0 0 0 0xffffffff>;



		rng: rng@e3000 {

			compatible = "qcom,prng-ee";

			reg = <0x000e3000 0x1000>;

			clocks = <&gcc GCC_PRNG_AHB_CLK>;

			clock-names = "core";

		};



		tlmm: pinctrl@1000000 {

			compatible = "qcom,ipq9574-tlmm";

			reg = <0x01000000 0x300000>;
@@ -178,6 +185,36 @@ sdhc_1: mmc@7804000 { 
			status = "disabled";

		};



		blsp_dma: dma-controller@7884000 {

			compatible = "qcom,bam-v1.7.0";

			reg = <0x07884000 0x2b000>;

			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "bam_clk";

			#dma-cells = <1>;

			qcom,ee = <0>;

		};



		blsp1_uart0: serial@78af000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x078af000 0x200>;

			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		blsp1_uart1: serial@78b0000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x078b0000 0x200>;

			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		blsp1_uart2: serial@78b1000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x078b1000 0x200>;
@@ -188,6 +225,163 @@ blsp1_uart2: serial@78b1000 { 
			status = "disabled";

		};



		blsp1_uart3: serial@78b2000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x078b2000 0x200>;

			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		blsp1_uart4: serial@78b3000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x078b3000 0x200>;

			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		blsp1_uart5: serial@78b4000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x078b4000 0x200>;

			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		blsp1_spi0: spi@78b5000 {

			compatible = "qcom,spi-qup-v2.2.1";

			reg = <0x078b5000 0x600>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			dmas = <&blsp_dma 12>, <&blsp_dma 13>;

			dma-names = "tx", "rx";

			status = "disabled";

		};



		blsp1_i2c1: i2c@78b6000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b6000 0x600>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			dmas = <&blsp_dma 14>, <&blsp_dma 15>;

			dma-names = "tx", "rx";

			status = "disabled";

		};



		blsp1_spi1: spi@78b6000 {

			compatible = "qcom,spi-qup-v2.2.1";

			reg = <0x078b6000 0x600>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			dmas = <&blsp_dma 14>, <&blsp_dma 15>;

			dma-names = "tx", "rx";

			status = "disabled";

		};



		blsp1_i2c2: i2c@78b7000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b7000 0x600>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			dmas = <&blsp_dma 16>, <&blsp_dma 17>;

			dma-names = "tx", "rx";

			status = "disabled";

		};



		blsp1_spi2: spi@78b7000 {

			compatible = "qcom,spi-qup-v2.2.1";

			reg = <0x078b7000 0x600>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			dmas = <&blsp_dma 16>, <&blsp_dma 17>;

			dma-names = "tx", "rx";

			status = "disabled";

		};



		blsp1_i2c3: i2c@78b8000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b8000 0x600>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			dmas = <&blsp_dma 18>, <&blsp_dma 19>;

			dma-names = "tx", "rx";

			status = "disabled";

		};



		blsp1_spi3: spi@78b8000 {

			compatible = "qcom,spi-qup-v2.2.1";

			reg = <0x078b8000 0x600>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			spi-max-frequency = <50000000>;

			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			dmas = <&blsp_dma 18>, <&blsp_dma 19>;

			dma-names = "tx", "rx";

			status = "disabled";

		};



		blsp1_i2c4: i2c@78b9000 {

			compatible = "qcom,i2c-qup-v2.2.1";

			reg = <0x078b9000 0x600>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			dmas = <&blsp_dma 20>, <&blsp_dma 21>;

			dma-names = "tx", "rx";

			status = "disabled";

		};



		blsp1_spi4: spi@78b9000 {

			compatible = "qcom,spi-qup-v2.2.1";

			reg = <0x078b9000 0x600>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			dmas = <&blsp_dma 20>, <&blsp_dma 21>;

			dma-names = "tx", "rx";

			status = "disabled";

		};



		intc: interrupt-controller@b000000 {

			compatible = "qcom,msm-qgic2";

			reg = <0x0b000000 0x1000>,  /* GICD */
@@ -220,6 +414,14 @@ v2m2: v2m@2000 { 
			};

		};



		watchdog: watchdog@b017000 {

			compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";

			reg = <0x0b017000 0x1000>;

			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;

			clocks = <&sleep_clk>;

			timeout-sec = <30>;

		};



		timer@b120000 {

			compatible = "arm,armv7-timer-mem";

			reg = <0x0b120000 0x1000>;