Merge tag 'omap-for-v5.16/gpmc-signed' of... (9f2feb32) · Commits · jan.koester / Linux

Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

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	Device tree bindings for OMAP general purpose memory controllers (GPMC)

	The actual devices are instantiated from the child nodes of a GPMC node.

	Required properties:

	- compatible: Should be set to one of the following:

	ti,omap2420-gpmc (omap2420)
	ti,omap2430-gpmc (omap2430)
	ti,omap3430-gpmc (omap3430 & omap3630)
	ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
	ti,am3352-gpmc (am335x devices)

	- reg: A resource specifier for the register space
	(see the example below)
	- ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
	completed.
	- #address-cells: Must be set to 2 to allow memory address translation
	- #size-cells: Must be set to 1 to allow CS address passing
	- gpmc,num-cs: The maximum number of chip-select lines that controller
	can support.
	- gpmc,num-waitpins: The maximum number of wait pins that controller can
	support.
	- ranges: Must be set up to reflect the memory layout with four
	integer values for each chip-select line in use:

	<cs-number> 0 <physical address of mapping> <size>

	Currently, calculated values derived from the contents
	of the per-CS register GPMC_CONFIG7 (as set up by the
	bootloader) are used for the physical address decoding.
	As this will change in the future, filling correct
	values here is a requirement.
	- interrupt-controller: The GPMC driver implements and interrupt controller for
	the NAND events "fifoevent" and "termcount" plus the
	rising/falling edges on the GPMC_WAIT pins.
	The interrupt number mapping is as follows
	0 - NAND_fifoevent
	1 - NAND_termcount
	2 - GPMC_WAIT0 pin edge
	3 - GPMC_WAIT1 pin edge, and so on.
	- interrupt-cells: Must be set to 2
	- gpio-controller: The GPMC driver implements a GPIO controller for the
	GPMC WAIT pins that can be used as general purpose inputs.
	0 maps to GPMC_WAIT0 pin.
	- gpio-cells: Must be set to 2

	Required properties when using NAND prefetch dma:
	- dmas GPMC NAND prefetch dma channel
	- dma-names Must be set to "rxtx"

	Timing properties for child nodes. All are optional and default to 0.

	- gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds

	Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
	- gpmc,cs-on-ns: Assertion time
	- gpmc,cs-rd-off-ns: Read deassertion time
	- gpmc,cs-wr-off-ns: Write deassertion time

	ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
	- gpmc,adv-on-ns: Assertion time
	- gpmc,adv-rd-off-ns: Read deassertion time
	- gpmc,adv-wr-off-ns: Write deassertion time
	- gpmc,adv-aad-mux-on-ns: Assertion time for AAD
	- gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD
	- gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD

	WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
	- gpmc,we-on-ns Assertion time
	- gpmc,we-off-ns: Deassertion time

	OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
	- gpmc,oe-on-ns: Assertion time
	- gpmc,oe-off-ns: Deassertion time
	- gpmc,oe-aad-mux-on-ns: Assertion time for AAD
	- gpmc,oe-aad-mux-off-ns: Deassertion time for AAD

	Access time and cycle time timings (in nanoseconds) corresponding to
	GPMC_CONFIG5:
	- gpmc,page-burst-access-ns: Multiple access word delay
	- gpmc,access-ns: Start-cycle to first data valid delay
	- gpmc,rd-cycle-ns: Total read cycle time
	- gpmc,wr-cycle-ns: Total write cycle time
	- gpmc,bus-turnaround-ns: Turn-around time between successive accesses
	- gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
	- gpmc,clk-activation-ns: GPMC clock activation time
	- gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
	data

	Boolean timing parameters. If property is present parameter enabled and
	disabled if omitted:
	- gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
	- gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
	- gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
	accesses to a different CS
	- gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
	accesses to the same CS
	- gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
	- gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
	- gpmc,time-para-granularity: Multiply all access times by 2

	The following are only applicable to OMAP3+ and AM335x:
	- gpmc,wr-access-ns: In synchronous write mode, for single or
	burst accesses, defines the number of
	GPMC_FCLK cycles from start access time
	to the GPMC_CLK rising edge used by the
	memory device for the first data capture.
	- gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
	the time when the first data is driven on
	the address-data bus.

	GPMC chip-select settings properties for child nodes. All are optional.

	- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
	- gpmc,burst-wrap Enables wrap bursting
	- gpmc,burst-read Enables read page/burst mode
	- gpmc,burst-write Enables write page/burst mode
	- gpmc,device-width Total width of device(s) connected to a GPMC
	chip-select in bytes. The GPMC supports 8-bit
	and 16-bit devices and so this property must be
	1 or 2.
	- gpmc,mux-add-data Address and data multiplexing configuration.
	Valid values are 1 for address-address-data
	multiplexing mode and 2 for address-data
	multiplexing mode.
	- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
	is this is not set.
	- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
	is this is not set.
	- gpmc,wait-pin Wait-pin used by client. Must be less than
	"gpmc,num-waitpins".
	- gpmc,wait-on-read Enables wait monitoring on reads.
	- gpmc,wait-on-write Enables wait monitoring on writes.

	Example for an AM33xx board:

	gpmc: gpmc@50000000 {
	compatible = "ti,am3352-gpmc";
	ti,hwmods = "gpmc";
	reg = <0x50000000 0x2000>;
	interrupts = <100>;
	dmas = <&edma 52 0>;
	dma-names = "rxtx";
	gpmc,num-cs = <8>;
	gpmc,num-waitpins = <2>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-controller;
	#gpio-cells = <2>;

	/* child nodes go here */
	};

Documentation/devicetree/bindings/memory-controllers/ti,gpmc-child.yaml

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			# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			%YAML 1.2
			---
			$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
			$schema: http://devicetree.org/meta-schemas/core.yaml#

			title: device tree bindings for children of the Texas Instruments GPMC

			maintainers:
			- Tony Lindgren <tony@atomide.com>
			- Roger Quadros <rogerq@kernel.org>

			description:
			This binding is meant for the child nodes of the GPMC node. The node
			represents any device connected to the GPMC bus. It may be a Flash chip,
			RAM chip or Ethernet controller, etc. These properties are meant for
			configuring the GPMC settings/timings and will accompany the bindings
			supported by the respective device.

			properties:
			reg: true

			# GPMC Timing properties for child nodes. All are optional and default to 0.
			gpmc,sync-clk-ps:
			description: Minimum clock period for synchronous mode
			default: 0

			# Chip-select signal timings corresponding to GPMC_CONFIG2:
			gpmc,cs-on-ns:
			description: Assertion time
			default: 0

			gpmc,cs-rd-off-ns:
			description: Read deassertion time
			default: 0

			gpmc,cs-wr-off-ns:
			description: Write deassertion time
			default: 0

			# ADV signal timings corresponding to GPMC_CONFIG3:
			gpmc,adv-on-ns:
			description: Assertion time
			default: 0

			gpmc,adv-rd-off-ns:
			description: Read deassertion time
			default: 0

			gpmc,adv-wr-off-ns:
			description: Write deassertion time
			default: 0

			gpmc,adv-aad-mux-on-ns:
			description: Assertion time for AAD
			default: 0

			gpmc,adv-aad-mux-rd-off-ns:
			description: Read deassertion time for AAD
			default: 0

			gpmc,adv-aad-mux-wr-off-ns:
			description: Write deassertion time for AAD
			default: 0

			# WE signals timings corresponding to GPMC_CONFIG4:
			gpmc,we-on-ns:
			description: Assertion time
			default: 0

			gpmc,we-off-ns:
			description: Deassertion time
			default: 0

			# OE signals timings corresponding to GPMC_CONFIG4:
			gpmc,oe-on-ns:
			description: Assertion time
			default: 0

			gpmc,oe-off-ns:
			description: Deassertion time
			default: 0

			gpmc,oe-aad-mux-on-ns:
			description: Assertion time for AAD
			default: 0

			gpmc,oe-aad-mux-off-ns:
			description: Deassertion time for AAD
			default: 0

			# Access time and cycle time timings (in nanoseconds) corresponding to
			# GPMC_CONFIG5:
			gpmc,page-burst-access-ns:
			description: Multiple access word delay
			default: 0

			gpmc,access-ns:
			description: Start-cycle to first data valid delay
			default: 0

			gpmc,rd-cycle-ns:
			description: Total read cycle time
			default: 0

			gpmc,wr-cycle-ns:
			description: Total write cycle time
			default: 0

			gpmc,bus-turnaround-ns:
			description: Turn-around time between successive accesses
			default: 0

			gpmc,cycle2cycle-delay-ns:
			description: Delay between chip-select pulses
			default: 0

			gpmc,clk-activation-ns:
			description: GPMC clock activation time
			default: 0

			gpmc,wait-monitoring-ns:
			description: Start of wait monitoring with regard to valid data
			default: 0

			# Boolean timing parameters. If property is present, parameter is enabled
			# otherwise disabled.
			gpmc,adv-extra-delay:
			description: ADV signal is delayed by half GPMC clock
			type: boolean

			gpmc,cs-extra-delay:
			description: CS signal is delayed by half GPMC clock
			type: boolean

			gpmc,cycle2cycle-diffcsen:
			description: \|
			Add "cycle2cycle-delay" between successive accesses
			to a different CS
			type: boolean

			gpmc,cycle2cycle-samecsen:
			description: \|
			Add "cycle2cycle-delay" between successive accesses
			to the same CS
			type: boolean

			gpmc,oe-extra-delay:
			description: OE signal is delayed by half GPMC clock
			type: boolean

			gpmc,we-extra-delay:
			description: WE signal is delayed by half GPMC clock
			type: boolean

			gpmc,time-para-granularity:
			description: Multiply all access times by 2
			type: boolean

			# The following two properties are applicable only to OMAP3+ and AM335x:
			gpmc,wr-access-ns:
			description: \|
			In synchronous write mode, for single or
			burst accesses, defines the number of
			GPMC_FCLK cycles from start access time
			to the GPMC_CLK rising edge used by the
			memory device for the first data capture.
			default: 0

			gpmc,wr-data-mux-bus-ns:
			description: \|
			In address-data multiplex mode, specifies
			the time when the first data is driven on
			the address-data bus.
			default: 0

			# GPMC chip-select settings properties for child nodes. All are optional.
			gpmc,burst-length:
			description: Page/burst length.
			$ref: /schemas/types.yaml#/definitions/uint32
			enum: [0, 4, 8, 16]
			default: 0

			gpmc,burst-wrap:
			description: Enables wrap bursting
			type: boolean

			gpmc,burst-read:
			description: Enables read page/burst mode
			type: boolean

			gpmc,burst-write:
			description: Enables write page/burst mode
			type: boolean

			gpmc,device-width:
			description: \|
			Total width of device(s) connected to a GPMC
			chip-select in bytes. The GPMC supports 8-bit
			and 16-bit devices and so this property must be
			1 or 2.
			$ref: /schemas/types.yaml#/definitions/uint32
			enum: [1, 2]
			default: 1

			gpmc,mux-add-data:
			description: \|
			Address and data multiplexing configuration.
			Valid values are
			0 for Non multiplexed mode
			1 for address-address-data multiplexing mode and
			2 for address-data multiplexing mode.
			$ref: /schemas/types.yaml#/definitions/uint32
			enum: [0, 1, 2]

			gpmc,sync-read:
			description: \|
			Enables synchronous read. Defaults to asynchronous
			is this is not set.
			type: boolean

			gpmc,sync-write:
			description: \|
			Enables synchronous writes. Defaults to asynchronous
			is this is not set.
			type: boolean

			gpmc,wait-pin:
			description: \|
			Wait-pin used by client. Must be less than "gpmc,num-waitpins".
			$ref: /schemas/types.yaml#/definitions/uint32

			gpmc,wait-on-read:
			description: Enables wait monitoring on reads.
			type: boolean

			gpmc,wait-on-write:
			description: Enables wait monitoring on writes.
			type: boolean

			required:
			- reg

			# the GPMC child will have its own native properties
			additionalProperties: true

Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml

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			# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
			%YAML 1.2
			---
			$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
			$schema: http://devicetree.org/meta-schemas/core.yaml#

			title: Texas Instruments GPMC Memory Controller device-tree bindings

			maintainers:
			- Tony Lindgren <tony@atomide.com>
			- Roger Quadros <rogerq@kernel.org>

			description:
			The GPMC is a unified memory controller dedicated for interfacing
			with external memory devices like
			- Asynchronous SRAM-like memories and ASICs
			- Asynchronous, synchronous, and page mode burst NOR flash
			- NAND flash
			- Pseudo-SRAM devices

			properties:
			compatible:
			items:
			- enum:
			- ti,am3352-gpmc
			- ti,omap2420-gpmc
			- ti,omap2430-gpmc
			- ti,omap3430-gpmc
			- ti,omap4430-gpmc

			reg:
			maxItems: 1

			interrupts:
			maxItems: 1

			clocks:
			maxItems: 1
			description: \|
			Functional clock. Used for bus timing calculations and
			GPMC configuration.

			clock-names:
			items:
			- const: fck

			dmas:
			items:
			- description: DMA channel for GPMC NAND prefetch

			dma-names:
			items:
			- const: rxtx

			"#address-cells": true

			"#size-cells": true

			gpmc,num-cs:
			description: maximum number of supported chip-select lines.
			$ref: /schemas/types.yaml#/definitions/uint32

			gpmc,num-waitpins:
			description: maximum number of supported wait pins.
			$ref: /schemas/types.yaml#/definitions/uint32

			ranges:
			minItems: 1
			description: \|
			Must be set up to reflect the memory layout with four
			integer values for each chip-select line in use,
			<cs-number> 0 <physical address of mapping> <size>
			items:
			- description: NAND bank 0
			- description: NOR/SRAM bank 0
			- description: NOR/SRAM bank 1

			'#interrupt-cells':
			const: 2

			interrupt-controller:
			description: \|
			The GPMC driver implements and interrupt controller for
			the NAND events "fifoevent" and "termcount" plus the
			rising/falling edges on the GPMC_WAIT pins.
			The interrupt number mapping is as follows
			0 - NAND_fifoevent
			1 - NAND_termcount
			2 - GPMC_WAIT0 pin edge
			3 - GPMC_WAIT1 pin edge, and so on.

			'#gpio-cells':
			const: 2

			gpio-controller:
			description: \|
			The GPMC driver implements a GPIO controller for the
			GPMC WAIT pins that can be used as general purpose inputs.
			0 maps to GPMC_WAIT0 pin.

			ti,hwmods:
			description:
			Name of the HWMOD associated with GPMC. This is for legacy
			omap2/3 platforms only.
			$ref: /schemas/types.yaml#/definitions/string
			deprecated: true

			ti,no-idle-on-init:
			description:
			Prevent idling the module at init. This is for legacy omap2/3
			platforms only.
			type: boolean
			deprecated: true

			patternProperties:
			"@[0-7],[a-f0-9]+$":
			type: object
			description: \|
			The child device node represents the device connected to the GPMC
			bus. The device can be a NAND chip, SRAM device, NOR device
			or an ASIC.

			allOf:
			- $ref: "ti,gpmc-child.yaml"

			unevaluatedProperties: false

			required:
			- compatible
			- reg
			- gpmc,num-cs
			- gpmc,num-waitpins
			- "#address-cells"
			- "#size-cells"

			additionalProperties: false

			examples:
			- \|
			#include <dt-bindings/interrupt-controller/arm-gic.h>
			#include <dt-bindings/gpio/gpio.h>

			gpmc: memory-controller@50000000 {
			compatible = "ti,am3352-gpmc";
			reg = <0x50000000 0x2000>;
			interrupts = <100>;
			clocks = <&l3s_clkctrl>;
			clock-names = "fck";
			dmas = <&edma 52 0>;
			dma-names = "rxtx";
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <2>;
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;

			nand@0,0 {
			compatible = "ti,omap2-nand";
			reg = <0 0 4>;
			interrupt-parent = <&gpmc>;
			interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			<1 IRQ_TYPE_NONE>; /* termcount */
			ti,nand-xfer-type = "prefetch-dma";
			ti,nand-ecc-opt = "bch16";
			ti,elm-id = <&elm>;
			rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
			};
			};

Documentation/devicetree/bindings/mtd/gpmc-nand.txt

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	Device tree bindings for GPMC connected NANDs

	GPMC connected NAND (found on OMAP boards) are represented as child nodes of
	the GPMC controller with a name of "nand".

	All timing relevant properties as well as generic gpmc child properties are
	explained in a separate documents - please refer to
	Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

	For NAND specific properties such as ECC modes or bus width, please refer to
	Documentation/devicetree/bindings/mtd/nand-controller.yaml


	Required properties:

	- compatible: "ti,omap2-nand"
	- reg: range id (CS number), base offset and length of the
	NAND I/O space
	- interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.

	Optional properties:

	- nand-bus-width: Set this numeric value to 16 if the hardware
	is wired that way. If not specified, a bus
	width of 8 is assumed.

	- ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
	"sw" 1-bit Hamming ecc code via software
	"hw" <deprecated> use "ham1" instead
	"hw-romcode" <deprecated> use "ham1" instead
	"ham1" 1-bit Hamming ecc code
	"bch4" 4-bit BCH ecc code
	"bch8" 8-bit BCH ecc code
	"bch16" 16-bit BCH ECC code
	Refer below "How to select correct ECC scheme for your device ?"

	- ti,nand-xfer-type: A string setting the data transfer type. One of:

	"prefetch-polled" Prefetch polled mode (default)
	"polled" Polled mode, without prefetch
	"prefetch-dma" Prefetch enabled DMA mode
	"prefetch-irq" Prefetch enabled irq mode

	- elm_id: <deprecated> use "ti,elm-id" instead
	- ti,elm-id: Specifies phandle of the ELM devicetree node.
	ELM is an on-chip hardware engine on TI SoC which is used for
	locating ECC errors for BCHx algorithms. SoC devices which have
	ELM hardware engines should specify this device node in .dtsi
	Using ELM for ECC error correction frees some CPU cycles.
	- rb-gpios: GPIO specifier for the ready/busy# pin.

	For inline partition table parsing (optional):

	- #address-cells: should be set to 1
	- #size-cells: should be set to 1

	Example for an AM33xx board:

	gpmc: gpmc@50000000 {
	compatible = "ti,am3352-gpmc";
	ti,hwmods = "gpmc";
	reg = <0x50000000 0x36c>;
	interrupts = <100>;
	gpmc,num-cs = <8>;
	gpmc,num-waitpins = <2>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */
	elm_id = <&elm>;
	interrupt-controller;
	#interrupt-cells = <2>;

	nand@0,0 {
	compatible = "ti,omap2-nand";
	reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */
	interrupt-parent = <&gpmc>;
	interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;
	nand-bus-width = <16>;
	ti,nand-ecc-opt = "bch8";
	ti,nand-xfer-type = "polled";
	rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */

	gpmc,sync-clk-ps = <0>;
	gpmc,cs-on-ns = <0>;
	gpmc,cs-rd-off-ns = <44>;
	gpmc,cs-wr-off-ns = <44>;
	gpmc,adv-on-ns = <6>;
	gpmc,adv-rd-off-ns = <34>;
	gpmc,adv-wr-off-ns = <44>;
	gpmc,we-off-ns = <40>;
	gpmc,oe-off-ns = <54>;
	gpmc,access-ns = <64>;
	gpmc,rd-cycle-ns = <82>;
	gpmc,wr-cycle-ns = <82>;
	gpmc,wr-access-ns = <40>;
	gpmc,wr-data-mux-bus-ns = <0>;

	#address-cells = <1>;
	#size-cells = <1>;

	/* partitions go here */
	};
	};

	How to select correct ECC scheme for your device ?
	--------------------------------------------------
	Higher ECC scheme usually means better protection against bit-flips and
	increased system lifetime. However, selection of ECC scheme is dependent
	on various other factors also like;

	(1) support of built in hardware engines.
	Some legacy OMAP SoC do not have ELM harware engine, so those SoC cannot
	support ecc-schemes with hardware error-correction (BCHx_HW). However
	such SoC can use ecc-schemes with software library for error-correction
	(BCHx_HW_DETECTION_SW). The error correction capability with software
	library remains equivalent to their hardware counter-part, but there is
	slight CPU penalty when too many bit-flips are detected during reads.

	(2) Device parameters like OOBSIZE.
	Other factor which governs the selection of ecc-scheme is oob-size.
	Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
	so the device should have enough free bytes available its OOB/Spare
	area to accommodate ECC for entire page. In general following expression
	helps in determining if given device can accommodate ECC syndrome:
	"2 + (PAGESIZE / 512) * ECC_BYTES" <= OOBSIZE"
	where
	OOBSIZE number of bytes in OOB/spare area
	PAGESIZE number of bytes in main-area of device page
	ECC_BYTES number of ECC bytes generated to protect
	512 bytes of data, which is:
	'3' for HAM1_xx ecc schemes
	'7' for BCH4_xx ecc schemes
	'14' for BCH8_xx ecc schemes
	'26' for BCH16_xx ecc schemes

	Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 and
	trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
	Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
	which is greater than capacity of NAND device (OOBSIZE=64)
	Hence, BCH16 cannot be supported on given device. But it can
	probably use lower ecc-schemes like BCH8.

	Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and
	trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
	Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
	which can be accommodated in the OOB/Spare area of this device
	(OOBSIZE=128). So this device can use BCH16 ecc-scheme.

Documentation/devicetree/bindings/mtd/gpmc-nor.txt

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