Commit 9fa81099 authored by Alan Cox's avatar Alan Cox Committed by Greg Kroah-Hartman
Browse files

Staging: et131x: de-hungarianise a bit 



bOverrideAddress is write only so kill it rather than fix it

Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 8c5f20f3

drivers/staging/et131x/et1310_eeprom.c

+96 −96
Original line number Diff line number Diff line
@@ -137,34 +137,34 @@ 
 * Define macros that allow individual register values to be extracted from a

 * DWORD1 register grouping

 */

#define EXTRACT_DATA_REGISTER(x)    (uint8_t)(x & 0xFF)

#define EXTRACT_STATUS_REGISTER(x)  (uint8_t)((x >> 16) & 0xFF)

#define EXTRACT_CONTROL_REG(x)      (uint8_t)((x >> 8) & 0xFF)

#define EXTRACT_DATA_REGISTER(x)    (u8)(x & 0xFF)

#define EXTRACT_STATUS_REGISTER(x)  (u8)((x >> 16) & 0xFF)

#define EXTRACT_CONTROL_REG(x)      (u8)((x >> 8) & 0xFF)



/**

 * EepromWriteByte - Write a byte to the ET1310's EEPROM

 * @etdev: pointer to our private adapter structure

 * @unAddress: the address to write

 * @bData: the value to write

 * @unEepronId: the ID of the EEPROM

 * @unAddressingMode: how the EEPROM is to be accessed

 * @addr: the address to write

 * @data: the value to write

 * @eeprom_id: the ID of the EEPROM

 * @addrmode: how the EEPROM is to be accessed

 *

 * Returns SUCCESS or FAILURE

 */

int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress,

			uint8_t bData, uint32_t unEepromId,

			uint32_t unAddressingMode)

int EepromWriteByte(struct et131x_adapter *etdev, u32 addr,

			u8 data, u32 eeprom_id,

			u32 addrmode)

{

	struct pci_dev *pdev = etdev->pdev;

	int32_t nIndex;

	int32_t nRetries;

	int32_t nError = false;

	int32_t nI2CWriteActive = 0;

	int32_t nWriteSuccessful = 0;

	uint8_t bControl;

	uint8_t bStatus = 0;

	uint32_t unDword1 = 0;

	uint32_t unData = 0;

	int index;

	int retries;

	int err = 0;

	int i2c_wack = 0;

	int writeok = 0;

	u8 control;

	u8 status = 0;

	u32 dword1 = 0;

	u32 val = 0;



	/*

	 * The following excerpt is from "Serial EEPROM HW Design
@@ -215,89 +215,89 @@ int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress, 
	 */



	/* Step 1: */

	for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {

	for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {

		/* Read registers grouped in DWORD1 */

		if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,

					  &unDword1)) {

			nError = 1;

					  &dword1)) {

			err = 1;

			break;

		}



		bStatus = EXTRACT_STATUS_REGISTER(unDword1);

		status = EXTRACT_STATUS_REGISTER(dword1);



		if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&

			bStatus & LBCIF_STATUS_I2C_IDLE)

		if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL &&

			status & LBCIF_STATUS_I2C_IDLE)

			/* bits 1:0 are equal to 1 */

			break;

	}



	if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))

	if (err || (index >= MAX_NUM_REGISTER_POLLS))

		return FAILURE;



	/* Step 2: */

	bControl = 0;

	bControl |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE;

	control = 0;

	control |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE;



	if (unAddressingMode == DUAL_BYTE)

		bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;

	if (addrmode == DUAL_BYTE)

		control |= LBCIF_CONTROL_TWO_BYTE_ADDR;



	if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,

				  bControl)) {

				  control)) {

		return FAILURE;

	}



	nI2CWriteActive = 1;

	i2c_wack = 1;



	/* Prepare EEPROM address for Step 3 */

	unAddress |= (unAddressingMode == DUAL_BYTE) ?

	    (unEepromId << 16) : (unEepromId << 8);

	addr |= (addrmode == DUAL_BYTE) ?

	    (eeprom_id << 16) : (eeprom_id << 8);



	for (nRetries = 0; nRetries < MAX_NUM_WRITE_RETRIES; nRetries++) {

	for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {

		/* Step 3:*/

		if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,

					   unAddress)) {

					   addr)) {

			break;

		}



		/* Step 4: */

		if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER_OFFSET,

					  bData)) {

					  data)) {

			break;

		}



		/* Step 5: */

		for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {

		for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {

			/* Read registers grouped in DWORD1 */

			if (pci_read_config_dword(pdev,

						  LBCIF_DWORD1_GROUP_OFFSET,

						  &unDword1)) {

				nError = 1;

						  &dword1)) {

				err = 1;

				break;

			}



			bStatus = EXTRACT_STATUS_REGISTER(unDword1);

			status = EXTRACT_STATUS_REGISTER(dword1);



			if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&

				bStatus & LBCIF_STATUS_I2C_IDLE) {

			if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL &&

				status & LBCIF_STATUS_I2C_IDLE) {

				/* I2C write complete */

				break;

			}

		}



		if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))

		if (err || (index >= MAX_NUM_REGISTER_POLLS))

			break;



		/*

		 * Step 6: Don't break here if we are revision 1, this is

		 *	   so we do a blind write for load bug.

		 */

		if (bStatus & LBCIF_STATUS_GENERAL_ERROR

		if (status & LBCIF_STATUS_GENERAL_ERROR

		    && etdev->pdev->revision == 0) {

			break;

		}



		/* Step 7 */

		if (bStatus & LBCIF_STATUS_ACK_ERROR) {

		if (status & LBCIF_STATUS_ACK_ERROR) {

			/*

			 * This could be due to an actual hardware failure

			 * or the EEPROM may still be in its internal write
@@ -308,19 +308,19 @@ int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress, 
			continue;

		}



		nWriteSuccessful = 1;

		writeok = 1;

		break;

	}



	/* Step 8: */

	udelay(10);

	nIndex = 0;

	while (nI2CWriteActive) {

		bControl &= ~LBCIF_CONTROL_I2C_WRITE;

	index = 0;

	while (i2c_wack) {

		control &= ~LBCIF_CONTROL_I2C_WRITE;



		if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,

					  bControl)) {

			nWriteSuccessful = 0;

					  control)) {

			writeok = 0;

		}



		/* Do read until internal ACK_ERROR goes away meaning write
@@ -329,44 +329,44 @@ int32_t EepromWriteByte(struct et131x_adapter *etdev, uint32_t unAddress, 
		do {

			pci_write_config_dword(pdev,

					       LBCIF_ADDRESS_REGISTER_OFFSET,

					       unAddress);

					       addr);

			do {

				pci_read_config_dword(pdev,

					LBCIF_DATA_REGISTER_OFFSET, &unData);

			} while ((unData & 0x00010000) == 0);

		} while (unData & 0x00040000);

					LBCIF_DATA_REGISTER_OFFSET, &val);

			} while ((val & 0x00010000) == 0);

		} while (val & 0x00040000);



		bControl = EXTRACT_CONTROL_REG(unData);

		control = EXTRACT_CONTROL_REG(val);



		if (bControl != 0xC0 || nIndex == 10000)

		if (control != 0xC0 || index == 10000)

			break;



		nIndex++;

		index++;

	}



	return nWriteSuccessful ? SUCCESS : FAILURE;

	return writeok ? SUCCESS : FAILURE;

}



/**

 * EepromReadByte - Read a byte from the ET1310's EEPROM

 * @etdev: pointer to our private adapter structure

 * @unAddress: the address from which to read

 * @pbData: a pointer to a byte in which to store the value of the read

 * @unEepronId: the ID of the EEPROM

 * @unAddressingMode: how the EEPROM is to be accessed

 * @addr: the address from which to read

 * @pdata: a pointer to a byte in which to store the value of the read

 * @eeprom_id: the ID of the EEPROM

 * @addrmode: how the EEPROM is to be accessed

 *

 * Returns SUCCESS or FAILURE

 */

int32_t EepromReadByte(struct et131x_adapter *etdev, uint32_t unAddress,

		       uint8_t *pbData, uint32_t unEepromId,

		       uint32_t unAddressingMode)

int EepromReadByte(struct et131x_adapter *etdev, u32 addr,

		       u8 *pdata, u32 eeprom_id,

		       u32 addrmode)

{

	struct pci_dev *pdev = etdev->pdev;

	int32_t nIndex;

	int32_t nError = 0;

	uint8_t bControl;

	uint8_t bStatus = 0;

	uint32_t unDword1 = 0;

	int index;

	int err = 0;

	u8 control;

	u8 status = 0;

	u32 dword1 = 0;



	/*

	 * The following excerpt is from "Serial EEPROM HW Design
@@ -403,70 +403,70 @@ int32_t EepromReadByte(struct et131x_adapter *etdev, uint32_t unAddress, 
	 */



	/* Step 1: */

	for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {

	for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {

		/* Read registers grouped in DWORD1 */

		if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,

					  &unDword1)) {

			nError = 1;

					  &dword1)) {

			err = 1;

			break;

		}



		bStatus = EXTRACT_STATUS_REGISTER(unDword1);

		status = EXTRACT_STATUS_REGISTER(dword1);



		if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&

		    bStatus & LBCIF_STATUS_I2C_IDLE) {

		if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL &&

		    status & LBCIF_STATUS_I2C_IDLE) {

			/* bits 1:0 are equal to 1 */

			break;

		}

	}



	if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))

	if (err || (index >= MAX_NUM_REGISTER_POLLS))

		return FAILURE;



	/* Step 2: */

	bControl = 0;

	bControl |= LBCIF_CONTROL_LBCIF_ENABLE;

	control = 0;

	control |= LBCIF_CONTROL_LBCIF_ENABLE;



	if (unAddressingMode == DUAL_BYTE)

		bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;

	if (addrmode == DUAL_BYTE)

		control |= LBCIF_CONTROL_TWO_BYTE_ADDR;



	if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,

				  bControl)) {

				  control)) {

		return FAILURE;

	}



	/* Step 3: */

	unAddress |= (unAddressingMode == DUAL_BYTE) ?

	    (unEepromId << 16) : (unEepromId << 8);

	addr |= (addrmode == DUAL_BYTE) ?

	    (eeprom_id << 16) : (eeprom_id << 8);



	if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,

				   unAddress)) {

				   addr)) {

		return FAILURE;

	}



	/* Step 4: */

	for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {

	for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {

		/* Read registers grouped in DWORD1 */

		if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,

					  &unDword1)) {

			nError = 1;

					  &dword1)) {

			err = 1;

			break;

		}



		bStatus = EXTRACT_STATUS_REGISTER(unDword1);

		status = EXTRACT_STATUS_REGISTER(dword1);



		if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL

		    && bStatus & LBCIF_STATUS_I2C_IDLE) {

		if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL

		    && status & LBCIF_STATUS_I2C_IDLE) {

			/* I2C read complete */

			break;

		}

	}



	if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS))

	if (err || (index >= MAX_NUM_REGISTER_POLLS))

		return FAILURE;



	/* Step 6: */

	*pbData = EXTRACT_DATA_REGISTER(unDword1);

	*pdata = EXTRACT_DATA_REGISTER(dword1);



	return (bStatus & LBCIF_STATUS_ACK_ERROR) ? FAILURE : SUCCESS;

	return (status & LBCIF_STATUS_ACK_ERROR) ? FAILURE : SUCCESS;

}

drivers/staging/et131x/et1310_mac.c

+6 −6
Original line number Diff line number Diff line
@@ -195,7 +195,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev) 
	cfg2.value = readl(&pMac->cfg2.value);

	ifctrl.value = readl(&pMac->if_ctrl.value);



	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {

	if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {

		cfg2.bits.if_mode = 0x2;

		ifctrl.bits.phy_mode = 0x0;

	} else {
@@ -241,8 +241,8 @@ void ConfigMACRegs2(struct et131x_adapter *etdev) 
	}



	/* 1 - full duplex, 0 - half-duplex */

	cfg2.bits.full_duplex = etdev->uiDuplexMode;

	ifctrl.bits.ghd_mode = !etdev->uiDuplexMode;

	cfg2.bits.full_duplex = etdev->duplex_mode;

	ifctrl.bits.ghd_mode = !etdev->duplex_mode;



	writel(ifctrl.value, &pMac->if_ctrl.value);

	writel(cfg2.value, &pMac->cfg2.value);
@@ -262,7 +262,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev) 


	DBG_TRACE(et131x_dbginfo,

		"Speed %d, Dup %d, CFG1 0x%08x, CFG2 0x%08x, if_ctrl 0x%08x\n",

		etdev->uiLinkSpeed, etdev->uiDuplexMode,

		etdev->linkspeed, etdev->duplex_mode,

		readl(&pMac->cfg1.value), readl(&pMac->cfg2.value),

		readl(&pMac->if_ctrl.value));
@@ -408,7 +408,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) 
	 * bit 16: Receive frame truncated.

	 * bit 17: Drop packet enable

	 */

	if (etdev->uiLinkSpeed == TRUEPHY_SPEED_100MBPS)

	if (etdev->linkspeed == TRUEPHY_SPEED_100MBPS)

		writel(0x30038, &pRxMac->mif_ctrl.value);

	else

		writel(0x30030, &pRxMac->mif_ctrl.value);
@@ -540,7 +540,7 @@ void ConfigMacStatRegs(struct et131x_adapter *etdev) 


void ConfigFlowControl(struct et131x_adapter *etdev)

{

	if (etdev->uiDuplexMode == 0) {

	if (etdev->duplex_mode == 0) {

		etdev->FlowControl = None;

	} else {

		char RemotePause, RemoteAsyncPause;

drivers/staging/et131x/et1310_phy.c

+119 −119
Original line number Diff line number Diff line
@@ -477,13 +477,13 @@ static int et131x_xcvr_init(struct et131x_adapter *adapter) 
void et131x_Mii_check(struct et131x_adapter *etdev,

		      MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)

{

	uint8_t ucLinkStatus;

	uint32_t uiAutoNegStatus;

	uint32_t uiSpeed;

	uint32_t uiDuplex;

	uint32_t uiMdiMdix;

	uint32_t uiMasterSlave;

	uint32_t uiPolarity;

	uint8_t link_status;

	uint32_t autoneg_status;

	uint32_t speed;

	uint32_t duplex;

	uint32_t mdi_mdix;

	uint32_t masterslave;

	uint32_t polarity;

	unsigned long flags;



	DBG_ENTER(et131x_dbginfo);
@@ -509,7 +509,7 @@ void et131x_Mii_check(struct et131x_adapter *etdev, 
			DBG_WARNING(et131x_dbginfo,

				    "Link down cable problem\n");



			if (etdev->uiLinkSpeed == TRUEPHY_SPEED_10MBPS) {

			if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {

				/* NOTE - Is there a way to query this without

				 * TruePHY?

				 * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
@@ -546,8 +546,8 @@ void et131x_Mii_check(struct et131x_adapter *etdev, 
					netif_carrier_off(etdev->netdev);

			}



			etdev->uiLinkSpeed = 0;

			etdev->uiDuplexMode = 0;

			etdev->linkspeed = 0;

			etdev->duplexMode = 0;



			/* Free the packets being actively sent & stopped */

			et131x_free_busy_send_packets(etdev);
@@ -581,21 +581,21 @@ void et131x_Mii_check(struct et131x_adapter *etdev, 
	    (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {

		if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {

			ET1310_PhyLinkStatus(etdev,

					     &ucLinkStatus, &uiAutoNegStatus,

					     &uiSpeed, &uiDuplex, &uiMdiMdix,

					     &uiMasterSlave, &uiPolarity);

					     &link_status, &autoneg_status,

					     &speed, &duplex, &mdi_mdix,

					     &masterslave, &polarity);



			etdev->uiLinkSpeed = uiSpeed;

			etdev->uiDuplexMode = uiDuplex;

			etdev->linkspeed = speed;

			etdev->duplex_mode = duplex;



			DBG_TRACE(et131x_dbginfo,

				"etdev->uiLinkSpeed 0x%04x, etdev->uiDuplex 0x%08x\n",

				etdev->uiLinkSpeed,

				etdev->uiDuplexMode);

				"etdev->linkspeed 0x%04x, etdev->duplex_mode 0x%08x\n",

				etdev->linkspeed,

				etdev->duplex_mode);



			etdev->PoMgmt.TransPhyComaModeOnBoot = 20;



			if (etdev->uiLinkSpeed == TRUEPHY_SPEED_10MBPS) {

			if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {

				/*

				 * NOTE - Is there a way to query this without

				 * TruePHY?
@@ -612,7 +612,7 @@ void et131x_Mii_check(struct et131x_adapter *etdev, 


			ConfigFlowControl(etdev);



			if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS &&

			if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&

					etdev->RegistryJumboPacket > 2048)

				ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,

								   0x2000);
@@ -905,67 +905,67 @@ static const uint16_t ConfigPhy[25][2] = { 
/* condensed version of the phy initialization routine */

void ET1310_PhyInit(struct et131x_adapter *etdev)

{

	uint16_t usData, usIndex;

	uint16_t data, index;



	if (etdev == NULL)

		return;



	/* get the identity (again ?) */

	MiRead(etdev, PHY_ID_1, &usData);

	MiRead(etdev, PHY_ID_2, &usData);

	MiRead(etdev, PHY_ID_1, &data);

	MiRead(etdev, PHY_ID_2, &data);



	/* what does this do/achieve ? */

	MiRead(etdev, PHY_MPHY_CONTROL_REG, &usData); /* should read 0002 */

	MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */

	MiWrite(etdev, PHY_MPHY_CONTROL_REG,	0x0006);



	/* read modem register 0402, should I do something with the return

	   data ? */

	MiWrite(etdev, PHY_INDEX_REG, 0x0402);

	MiRead(etdev, PHY_DATA_REG, &usData);

	MiRead(etdev, PHY_DATA_REG, &data);



	/* what does this do/achieve ? */

	MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);



	/* get the identity (again ?) */

	MiRead(etdev, PHY_ID_1, &usData);

	MiRead(etdev, PHY_ID_2, &usData);

	MiRead(etdev, PHY_ID_1, &data);

	MiRead(etdev, PHY_ID_2, &data);



	/* what does this achieve ? */

	MiRead(etdev, PHY_MPHY_CONTROL_REG, &usData); /* should read 0002 */

	MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */

	MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);



	/* read modem register 0402, should I do something with

	   the return data? */

	MiWrite(etdev, PHY_INDEX_REG, 0x0402);

	MiRead(etdev, PHY_DATA_REG, &usData);

	MiRead(etdev, PHY_DATA_REG, &data);



	MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);



	/* what does this achieve (should return 0x1040) */

	MiRead(etdev, PHY_CONTROL, &usData);

	MiRead(etdev, PHY_MPHY_CONTROL_REG, &usData); /* should read 0002 */

	MiRead(etdev, PHY_CONTROL, &data);

	MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */

	MiWrite(etdev, PHY_CONTROL, 0x1840);



	MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);



	/* here the writing of the array starts.... */

	usIndex = 0;

	while (ConfigPhy[usIndex][0] != 0x0000) {

	index = 0;

	while (ConfigPhy[index][0] != 0x0000) {

		/* write value */

		MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[usIndex][0]);

		MiWrite(etdev, PHY_DATA_REG, ConfigPhy[usIndex][1]);

		MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);

		MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]);



		/* read it back */

		MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[usIndex][0]);

		MiRead(etdev, PHY_DATA_REG, &usData);

		MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);

		MiRead(etdev, PHY_DATA_REG, &data);



		/* do a check on the value read back ? */

		usIndex++;

		index++;

	}

	/* here the writing of the array ends... */



	MiRead(etdev, PHY_CONTROL, &usData);		/* 0x1840 */

	MiRead(etdev, PHY_MPHY_CONTROL_REG, &usData);/* should read 0007 */

	MiRead(etdev, PHY_CONTROL, &data);		/* 0x1840 */

	MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */

	MiWrite(etdev, PHY_CONTROL, 0x1040);

	MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);

}
@@ -977,64 +977,64 @@ void ET1310_PhyReset(struct et131x_adapter *etdev) 


void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)

{

	uint16_t usData;

	uint16_t data;



	MiRead(etdev, PHY_CONTROL, &usData);

	MiRead(etdev, PHY_CONTROL, &data);



	if (down == false) {

		/* Power UP */

		usData &= ~0x0800;

		MiWrite(etdev, PHY_CONTROL, usData);

		data &= ~0x0800;

		MiWrite(etdev, PHY_CONTROL, data);

	} else {

		/* Power DOWN */

		usData |= 0x0800;

		MiWrite(etdev, PHY_CONTROL, usData);

		data |= 0x0800;

		MiWrite(etdev, PHY_CONTROL, data);

	}

}



void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)

{

	uint16_t usData;

	uint16_t data;



	MiRead(etdev, PHY_CONTROL, &usData);

	MiRead(etdev, PHY_CONTROL, &data);



	if (enable == true) {

		/* Autonegotiation ON */

		usData |= 0x1000;

		MiWrite(etdev, PHY_CONTROL, usData);

		data |= 0x1000;

		MiWrite(etdev, PHY_CONTROL, data);

	} else {

		/* Autonegotiation OFF */

		usData &= ~0x1000;

		MiWrite(etdev, PHY_CONTROL, usData);

		data &= ~0x1000;

		MiWrite(etdev, PHY_CONTROL, data);

	}

}



void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, uint16_t duplex)

{

	uint16_t usData;

	uint16_t data;



	MiRead(etdev, PHY_CONTROL, &usData);

	MiRead(etdev, PHY_CONTROL, &data);



	if (duplex == TRUEPHY_DUPLEX_FULL) {

		/* Set Full Duplex */

		usData |= 0x100;

		MiWrite(etdev, PHY_CONTROL, usData);

		data |= 0x100;

		MiWrite(etdev, PHY_CONTROL, data);

	} else {

		/* Set Half Duplex */

		usData &= ~0x100;

		MiWrite(etdev, PHY_CONTROL, usData);

		data &= ~0x100;

		MiWrite(etdev, PHY_CONTROL, data);

	}

}



void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, uint16_t speed)

{

	uint16_t usData;

	uint16_t data;



	/* Read the PHY control register */

	MiRead(etdev, PHY_CONTROL, &usData);

	MiRead(etdev, PHY_CONTROL, &data);



	/* Clear all Speed settings (Bits 6, 13) */

	usData &= ~0x2040;

	data &= ~0x2040;



	/* Reset the speed bits based on user selection */

	switch (speed) {
@@ -1044,29 +1044,29 @@ void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, uint16_t speed) 


	case TRUEPHY_SPEED_100MBPS:

		/* 100M == Set bit 13 */

		usData |= 0x2000;

		data |= 0x2000;

		break;



	case TRUEPHY_SPEED_1000MBPS:

	default:

		usData |= 0x0040;

		data |= 0x0040;

		break;

	}



	/* Write back the new speed */

	MiWrite(etdev, PHY_CONTROL, usData);

	MiWrite(etdev, PHY_CONTROL, data);

}



void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,

				  uint16_t duplex)

{

	uint16_t usData;

	uint16_t data;



	/* Read the PHY 1000 Base-T Control Register */

	MiRead(etdev, PHY_1000_CONTROL, &usData);

	MiRead(etdev, PHY_1000_CONTROL, &data);



	/* Clear Bits 8,9 */

	usData &= ~0x0300;

	data &= ~0x0300;



	switch (duplex) {

	case TRUEPHY_ADV_DUPLEX_NONE:
@@ -1075,34 +1075,34 @@ void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev, 


	case TRUEPHY_ADV_DUPLEX_FULL:

		/* Set Bit 9 */

		usData |= 0x0200;

		data |= 0x0200;

		break;



	case TRUEPHY_ADV_DUPLEX_HALF:

		/* Set Bit 8 */

		usData |= 0x0100;

		data |= 0x0100;

		break;



	case TRUEPHY_ADV_DUPLEX_BOTH:

	default:

		usData |= 0x0300;

		data |= 0x0300;

		break;

	}



	/* Write back advertisement */

	MiWrite(etdev, PHY_1000_CONTROL, usData);

	MiWrite(etdev, PHY_1000_CONTROL, data);

}



void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,

				 uint16_t duplex)

{

	uint16_t usData;

	uint16_t data;



	/* Read the Autonegotiation Register (10/100) */

	MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &usData);

	MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);



	/* Clear bits 7,8 */

	usData &= ~0x0180;

	data &= ~0x0180;



	switch (duplex) {

	case TRUEPHY_ADV_DUPLEX_NONE:
@@ -1111,35 +1111,35 @@ void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev, 


	case TRUEPHY_ADV_DUPLEX_FULL:

		/* Set Bit 8 */

		usData |= 0x0100;

		data |= 0x0100;

		break;



	case TRUEPHY_ADV_DUPLEX_HALF:

		/* Set Bit 7 */

		usData |= 0x0080;

		data |= 0x0080;

		break;



	case TRUEPHY_ADV_DUPLEX_BOTH:

	default:

		/* Set Bits 7,8 */

		usData |= 0x0180;

		data |= 0x0180;

		break;

	}



	/* Write back advertisement */

	MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, usData);

	MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);

}



void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,

				uint16_t duplex)

{

	uint16_t usData;

	uint16_t data;



	/* Read the Autonegotiation Register (10/100) */

	MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &usData);

	MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);



	/* Clear bits 5,6 */

	usData &= ~0x0060;

	data &= ~0x0060;



	switch (duplex) {

	case TRUEPHY_ADV_DUPLEX_NONE:
@@ -1148,75 +1148,75 @@ void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev, 


	case TRUEPHY_ADV_DUPLEX_FULL:

		/* Set Bit 6 */

		usData |= 0x0040;

		data |= 0x0040;

		break;



	case TRUEPHY_ADV_DUPLEX_HALF:

		/* Set Bit 5 */

		usData |= 0x0020;

		data |= 0x0020;

		break;



	case TRUEPHY_ADV_DUPLEX_BOTH:

	default:

		/* Set Bits 5,6 */

		usData |= 0x0060;

		data |= 0x0060;

		break;

	}



	/* Write back advertisement */

	MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, usData);

	MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);

}



void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,

			  uint8_t *ucLinkStatus,

			  uint32_t *uiAutoNeg,

			  uint32_t *uiLinkSpeed,

			  uint32_t *uiDuplexMode,

			  uint32_t *uiMdiMdix,

			  uint32_t *uiMasterSlave, uint32_t *uiPolarity)

			  uint8_t *link_status,

			  uint32_t *autoneg,

			  uint32_t *linkspeed,

			  uint32_t *duplex_mode,

			  uint32_t *mdi_mdix,

			  uint32_t *masterslave, uint32_t *polarity)

{

	uint16_t usMiStatus = 0;

	uint16_t us1000BaseT = 0;

	uint16_t usVmiPhyStatus = 0;

	uint16_t usControl = 0;



	MiRead(etdev, PHY_STATUS, &usMiStatus);

	MiRead(etdev, PHY_1000_STATUS, &us1000BaseT);

	MiRead(etdev, PHY_PHY_STATUS, &usVmiPhyStatus);

	MiRead(etdev, PHY_CONTROL, &usControl);



	if (ucLinkStatus) {

		*ucLinkStatus =

		    (unsigned char)((usVmiPhyStatus & 0x0040) ? 1 : 0);

	uint16_t mistatus = 0;

	uint16_t is1000BaseT = 0;

	uint16_t vmi_phystatus = 0;

	uint16_t control = 0;



	MiRead(etdev, PHY_STATUS, &mistatus);

	MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);

	MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);

	MiRead(etdev, PHY_CONTROL, &control);



	if (link_status) {

		*link_status =

		    (unsigned char)((vmi_phystatus & 0x0040) ? 1 : 0);

	}



	if (uiAutoNeg) {

		*uiAutoNeg =

		    (usControl & 0x1000) ? ((usVmiPhyStatus & 0x0020) ?

	if (autoneg) {

		*autoneg =

		    (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?

					    TRUEPHY_ANEG_COMPLETE :

					    TRUEPHY_ANEG_NOT_COMPLETE) :

		    TRUEPHY_ANEG_DISABLED;

	}



	if (uiLinkSpeed)

		*uiLinkSpeed = (usVmiPhyStatus & 0x0300) >> 8;

	if (linkspeed)

		*linkspeed = (vmi_phystatus & 0x0300) >> 8;



	if (uiDuplexMode)

		*uiDuplexMode = (usVmiPhyStatus & 0x0080) >> 7;

	if (duplex_mode)

		*duplex_mode = (vmi_phystatus & 0x0080) >> 7;



	if (uiMdiMdix)

	if (mdi_mdix)

		/* NOTE: Need to complete this */

		*uiMdiMdix = 0;

		*mdi_mdix = 0;



	if (uiMasterSlave) {

		*uiMasterSlave =

		    (us1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER :

	if (masterslave) {

		*masterslave =

		    (is1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER :

		    TRUEPHY_CFG_SLAVE;

	}



	if (uiPolarity) {

		*uiPolarity =

		    (usVmiPhyStatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED :

	if (polarity) {

		*polarity =

		    (vmi_phystatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED :

		    TRUEPHY_POLARITY_NORMAL;

	}

}

drivers/staging/et131x/et1310_phy.h

+6 −6
Original line number Diff line number Diff line
@@ -895,12 +895,12 @@ void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *adapter, 
void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *adapter,

				u16 duplex);

void ET1310_PhyLinkStatus(struct et131x_adapter *adapter,

			  u8 *ucLinkStatus,

			  u32 *uiAutoNeg,

			  u32 *uiLinkSpeed,

			  u32 *uiDuplexMode,

			  u32 *uiMdiMdix,

			  u32 *uiMasterSlave, u32 *uiPolarity);

			  u8 *Link_status,

			  u32 *autoneg,

			  u32 *linkspeed,

			  u32 *duplex_mode,

			  u32 *mdi_mdix,

			  u32 *masterslave, u32 *polarity);

void ET1310_PhyAndOrReg(struct et131x_adapter *adapter,

			u16 regnum, u16 andMask, u16 orMask);

void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter,

drivers/staging/et131x/et1310_rx.c

+68 −68

File changed.

Preview size limit exceeded, changes collapsed.