Commit a0061fc2 authored by Pramod Kumar's avatar Pramod Kumar Committed by Florian Fainelli
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arm64: dts: Update Stingray clock DT nodes 



Update clock output names in the Stingray clock DT nodes so they match
the binding document and the latest ASIC datasheet. Also add entries
for LCPLL2

Signed-off-by: default avatarPramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: default avatarRay Jui <ray.jui@broadcom.com>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent 8dd970a2

arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi

+19 −7
Original line number Diff line number Diff line
@@ -52,12 +52,24 @@ genpll0: genpll0@1d104 { 
			reg = <0x0001d104 0x32>,

			      <0x0001c854 0x4>;

			clocks = <&osc>;

			clock-output-names = "genpll0", "clk_125", "clk_scr",

			clock-output-names = "genpll0", "clk_125m", "clk_scr",

					     "clk_250", "clk_pcie_axi",

					     "clk_paxc_axi_x2",

					     "clk_paxc_axi";

		};



		genpll2: genpll2@1d1ac {

			#clock-cells = <1>;

			compatible = "brcm,sr-genpll2";

			reg = <0x0001d1ac 0x32>,

			      <0x0001c854 0x4>;

			clocks = <&osc>;

			clock-output-names = "genpll2", "clk_nic",

					     "clk_ts_500_ref", "clk_125_nitro",

					     "clk_chimp", "clk_nic_flash",

					     "clk_fs";

		};



		genpll3: genpll3@1d1e0 {

			#clock-cells = <1>;

			compatible = "brcm,sr-genpll3";
@@ -75,8 +87,8 @@ genpll4: genpll4@1d214 { 
			      <0x0001c854 0x4>;

			clocks = <&osc>;

			clock-output-names = "genpll4", "clk_ccn",

					     "clk_tpiu_pll", "noc_clk",

					     "pll_chclk_fs4",

					     "clk_tpiu_pll", "clk_noc",

					     "clk_chclk_fs4",

					     "clk_bridge_fscpu";

		};
@@ -86,8 +98,8 @@ genpll5: genpll5@1d248 { 
			reg = <0x0001d248 0x32>,

			      <0x0001c870 0x4>;

			clocks = <&osc>;

			clock-output-names = "genpll5", "fs4_hf_clk",

					     "crypto_ae_clk", "raid_ae_clk";

			clock-output-names = "genpll5", "clk_fs4_hf",

					     "clk_crypto_ae", "clk_raid_ae";

		};



		lcpll0: lcpll0@1d0c4 {
@@ -107,9 +119,9 @@ lcpll1: lcpll1@1d138 { 
			reg = <0x0001d138 0x3c>,

			      <0x0001c870 0x4>;

			clocks = <&osc>;

			clock-output-names = "lcpll1", "clk_wanpn",

			clock-output-names = "lcpll1", "clk_wan",

					     "clk_usb_ref",

					     "timesync_evt_clk";

					     "clk_crmu_ts";

		};



		hsls_clk: hsls_clk {