Commit a03d8b1e authored by Haojian Zhuang's avatar Haojian Zhuang
Browse files

ARM: mmp: enable tauros2 cache in pxa910 



Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
parent c2b7e05c

arch/arm/boot/dts/pxa910.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -25,6 +25,11 @@ soc { 
		interrupt-parent = <&intc>;

		ranges;



		L2: l2-cache {

			compatible = "marvell,tauros2-cache";

			marvell,tauros2-cache-features = <0x3>;

		};



		axi@d4200000 {	/* AXI */

			compatible = "mrvl,axi-bus", "simple-bus";

			#address-cells = <1>;

arch/arm/mach-mmp/pxa910.c

+4 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <linux/io.h>

#include <linux/platform_device.h>



#include <asm/hardware/cache-tauros2.h>

#include <asm/mach/time.h>

#include <mach/addr-map.h>

#include <mach/regs-apbc.h>
@@ -116,6 +117,9 @@ static struct clk_lookup pxa910_clkregs[] = { 
static int __init pxa910_init(void)

{

	if (cpu_is_pxa910()) {

#ifdef CONFIG_CACHE_TAUROS2

		tauros2_init(0);

#endif

		mfp_init_base(MFPR_VIRT_BASE);

		mfp_init_addr(pxa910_mfp_addr_map);

		pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);