Commit a03e3cb1 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: fix clock sequence logic for DCN32



[Why&How]
The newer commit sequence on DCN32 onwards did not finish clock
optimization sequence since the newer sequence did not end up calling
dc_post_update_surfaces_to_stream() which resets dc->optimized_required.

Call this function before passing control on to the new commit sequence.

Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 32953485
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+12 −6
Original line number Diff line number Diff line
@@ -4142,24 +4142,30 @@ void dc_commit_updates_for_stream(struct dc *dc,
	struct dc_context *dc_ctx = dc->ctx;
	int i, j;

	stream_status = dc_stream_get_status(stream);
	context = dc->current_state;

	update_type = dc_check_update_surfaces_for_stream(
				dc, srf_updates, surface_count, stream_update, stream_status);

	/* TODO: Since change commit sequence can have a huge impact,
	 * we decided to only enable it for DCN3x. However, as soon as
	 * we get more confident about this change we'll need to enable
	 * the new sequence for all ASICs.
	 */
	if (dc->ctx->dce_version >= DCN_VERSION_3_2) {
		/*
		 * Previous frame finished and HW is ready for optimization.
		 */
		if (update_type == UPDATE_TYPE_FAST)
			dc_post_update_surfaces_to_stream(dc);

		dc_update_planes_and_stream(dc, srf_updates,
					    surface_count, stream,
					    stream_update);
		return;
	}

	stream_status = dc_stream_get_status(stream);
	context = dc->current_state;

	update_type = dc_check_update_surfaces_for_stream(
				dc, srf_updates, surface_count, stream_update, stream_status);

	if (update_type >= update_surface_trace_level)
		update_surface_trace(dc, srf_updates, surface_count);