Commit a0936e9e authored Apr 22, 2023 by Krzysztof Kozlowski

arm64: dts: hisilicon: add missing cache properties

As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

hi3660-hikey960.dtb: l2-cache0: 'cache-unified' is a required property

Link: https://lore.kernel.org/r/20230421223215.115666-1-krzysztof.kozlowski@linaro.org

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

parent 9f921604

arch/arm64/boot/dts/hisilicon/hi3660.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -204,11 +204,13 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
		A53_L2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		A73_L2: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};

arch/arm64/boot/dts/hisilicon/hi6220.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -187,11 +187,13 @@ cpu7: cpu@103 {
		CLUSTER0_L2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		CLUSTER1_L2: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};

arch/arm64/boot/dts/hisilicon/hip05.dtsi

+4 −0

Original line number	Diff line number	Diff line
		@@ -212,21 +212,25 @@ cpu15: cpu@20303 {
		cluster0_l2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster1_l2: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster2_l2: l2-cache2 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster3_l2: l2-cache3 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};

arch/arm64/boot/dts/hisilicon/hip06.dtsi

+4 −0

Original line number	Diff line number	Diff line
		@@ -212,21 +212,25 @@ cpu15: cpu@10303 {
		cluster0_l2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster1_l2: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster2_l2: l2-cache2 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster3_l2: l2-cache3 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};

arch/arm64/boot/dts/hisilicon/hip07.dtsi

+16 −0

Original line number	Diff line number	Diff line
		@@ -843,81 +843,97 @@ cpu63: cpu@70303 {
		cluster0_l2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster1_l2: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster2_l2: l2-cache2 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster3_l2: l2-cache3 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster4_l2: l2-cache4 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster5_l2: l2-cache5 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster6_l2: l2-cache6 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster7_l2: l2-cache7 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster8_l2: l2-cache8 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster9_l2: l2-cache9 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster10_l2: l2-cache10 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster11_l2: l2-cache11 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster12_l2: l2-cache12 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster13_l2: l2-cache13 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster14_l2: l2-cache14 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};

		cluster15_l2: l2-cache15 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};