Loading arch/arm/mach-omap2/gpmc-nand.c +13 −13 Original line number Diff line number Diff line Loading @@ -52,27 +52,27 @@ static int omap2_nand_gpmc_retime( memset(&t, 0, sizeof(t)); t.sync_clk = gpmc_t->sync_clk; t.cs_on = gpmc_round_ns_to_ticks(gpmc_t->cs_on); t.adv_on = gpmc_round_ns_to_ticks(gpmc_t->adv_on); t.cs_on = gpmc_t->cs_on; t.adv_on = gpmc_t->adv_on; /* Read */ t.adv_rd_off = gpmc_round_ns_to_ticks(gpmc_t->adv_rd_off); t.adv_rd_off = gpmc_t->adv_rd_off; t.oe_on = t.adv_on; t.access = gpmc_round_ns_to_ticks(gpmc_t->access); t.oe_off = gpmc_round_ns_to_ticks(gpmc_t->oe_off); t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_t->cs_rd_off); t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_t->rd_cycle); t.access = gpmc_t->access; t.oe_off = gpmc_t->oe_off; t.cs_rd_off = gpmc_t->cs_rd_off; t.rd_cycle = gpmc_t->rd_cycle; /* Write */ t.adv_wr_off = gpmc_round_ns_to_ticks(gpmc_t->adv_wr_off); t.adv_wr_off = gpmc_t->adv_wr_off; t.we_on = t.oe_on; if (cpu_is_omap34xx()) { t.wr_data_mux_bus = gpmc_round_ns_to_ticks(gpmc_t->wr_data_mux_bus); t.wr_access = gpmc_round_ns_to_ticks(gpmc_t->wr_access); t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; t.wr_access = gpmc_t->wr_access; } t.we_off = gpmc_round_ns_to_ticks(gpmc_t->we_off); t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_t->cs_wr_off); t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_t->wr_cycle); t.we_off = gpmc_t->we_off; t.cs_wr_off = gpmc_t->cs_wr_off; t.wr_cycle = gpmc_t->wr_cycle; /* Configure GPMC */ if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) Loading Loading
arch/arm/mach-omap2/gpmc-nand.c +13 −13 Original line number Diff line number Diff line Loading @@ -52,27 +52,27 @@ static int omap2_nand_gpmc_retime( memset(&t, 0, sizeof(t)); t.sync_clk = gpmc_t->sync_clk; t.cs_on = gpmc_round_ns_to_ticks(gpmc_t->cs_on); t.adv_on = gpmc_round_ns_to_ticks(gpmc_t->adv_on); t.cs_on = gpmc_t->cs_on; t.adv_on = gpmc_t->adv_on; /* Read */ t.adv_rd_off = gpmc_round_ns_to_ticks(gpmc_t->adv_rd_off); t.adv_rd_off = gpmc_t->adv_rd_off; t.oe_on = t.adv_on; t.access = gpmc_round_ns_to_ticks(gpmc_t->access); t.oe_off = gpmc_round_ns_to_ticks(gpmc_t->oe_off); t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_t->cs_rd_off); t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_t->rd_cycle); t.access = gpmc_t->access; t.oe_off = gpmc_t->oe_off; t.cs_rd_off = gpmc_t->cs_rd_off; t.rd_cycle = gpmc_t->rd_cycle; /* Write */ t.adv_wr_off = gpmc_round_ns_to_ticks(gpmc_t->adv_wr_off); t.adv_wr_off = gpmc_t->adv_wr_off; t.we_on = t.oe_on; if (cpu_is_omap34xx()) { t.wr_data_mux_bus = gpmc_round_ns_to_ticks(gpmc_t->wr_data_mux_bus); t.wr_access = gpmc_round_ns_to_ticks(gpmc_t->wr_access); t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; t.wr_access = gpmc_t->wr_access; } t.we_off = gpmc_round_ns_to_ticks(gpmc_t->we_off); t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_t->cs_wr_off); t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_t->wr_cycle); t.we_off = gpmc_t->we_off; t.cs_wr_off = gpmc_t->cs_wr_off; t.wr_cycle = gpmc_t->wr_cycle; /* Configure GPMC */ if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) Loading