Commit a2d15ed7 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub number 



The number of GFXHUB/MMHUB may be expanded in later ASICs.

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3de2ff5d

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+2 −2
Original line number Diff line number Diff line
@@ -3060,12 +3060,12 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
	switch (args->in.op) {

	case AMDGPU_VM_OP_RESERVE_VMID:

		/* current, we only have requirement to reserve vmid from gfxhub */

		r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);

		r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);

		if (r)

			return r;

		break;

	case AMDGPU_VM_OP_UNRESERVE_VMID:

		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);

		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);

		break;

	default:

		return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+2 −2
Original line number Diff line number Diff line
@@ -101,8 +101,8 @@ struct amdgpu_bo_list_entry; 


/* max number of VMHUB */

#define AMDGPU_MAX_VMHUBS			2

#define AMDGPU_GFXHUB				0

#define AMDGPU_MMHUB				1

#define AMDGPU_GFXHUB_0				0

#define AMDGPU_MMHUB_0				1



/* hardcode that limit for now */

#define AMDGPU_VA_RESERVED_SIZE			(1ULL << 20)

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+4 −4
Original line number Diff line number Diff line
@@ -1603,7 +1603,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 
	/* XXX SH_MEM regs */

	/* where to put LDS, scratch, GPUVM in FSA64 space */

	mutex_lock(&adev->srbm_mutex);

	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {

	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {

		nv_grbm_select(adev, 0, 0, 0, i);

		/* CP and shaders */

		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
@@ -5005,7 +5005,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 
	.align_mask = 0xff,

	.nop = PACKET3(PACKET3_NOP, 0x3FFF),

	.support_64bit_ptrs = true,

	.vmhub = AMDGPU_GFXHUB,

	.vmhub = AMDGPU_GFXHUB_0,

	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,

	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,

	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
@@ -5056,7 +5056,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 
	.align_mask = 0xff,

	.nop = PACKET3(PACKET3_NOP, 0x3FFF),

	.support_64bit_ptrs = true,

	.vmhub = AMDGPU_GFXHUB,

	.vmhub = AMDGPU_GFXHUB_0,

	.get_rptr = gfx_v10_0_ring_get_rptr_compute,

	.get_wptr = gfx_v10_0_ring_get_wptr_compute,

	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
@@ -5089,7 +5089,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 
	.align_mask = 0xff,

	.nop = PACKET3(PACKET3_NOP, 0x3FFF),

	.support_64bit_ptrs = true,

	.vmhub = AMDGPU_GFXHUB,

	.vmhub = AMDGPU_GFXHUB_0,

	.get_rptr = gfx_v10_0_ring_get_rptr_compute,

	.get_wptr = gfx_v10_0_ring_get_wptr_compute,

	.set_wptr = gfx_v10_0_ring_set_wptr_compute,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+4 −4
Original line number Diff line number Diff line
@@ -1936,7 +1936,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 
	/* XXX SH_MEM regs */

	/* where to put LDS, scratch, GPUVM in FSA64 space */

	mutex_lock(&adev->srbm_mutex);

	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {

	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {

		soc15_grbm_select(adev, 0, 0, 0, i);

		/* CP and shaders */

		if (i == 0) {
@@ -5174,7 +5174,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 
	.align_mask = 0xff,

	.nop = PACKET3(PACKET3_NOP, 0x3FFF),

	.support_64bit_ptrs = true,

	.vmhub = AMDGPU_GFXHUB,

	.vmhub = AMDGPU_GFXHUB_0,

	.get_rptr = gfx_v9_0_ring_get_rptr_gfx,

	.get_wptr = gfx_v9_0_ring_get_wptr_gfx,

	.set_wptr = gfx_v9_0_ring_set_wptr_gfx,
@@ -5225,7 +5225,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 
	.align_mask = 0xff,

	.nop = PACKET3(PACKET3_NOP, 0x3FFF),

	.support_64bit_ptrs = true,

	.vmhub = AMDGPU_GFXHUB,

	.vmhub = AMDGPU_GFXHUB_0,

	.get_rptr = gfx_v9_0_ring_get_rptr_compute,

	.get_wptr = gfx_v9_0_ring_get_wptr_compute,

	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
@@ -5260,7 +5260,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 
	.align_mask = 0xff,

	.nop = PACKET3(PACKET3_NOP, 0x3FFF),

	.support_64bit_ptrs = true,

	.vmhub = AMDGPU_GFXHUB,

	.vmhub = AMDGPU_GFXHUB_0,

	.get_rptr = gfx_v9_0_ring_get_rptr_compute,

	.get_wptr = gfx_v9_0_ring_get_wptr_compute,

	.set_wptr = gfx_v9_0_ring_set_wptr_compute,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+1 −1
Original line number Diff line number Diff line
@@ -357,7 +357,7 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, 


void gfxhub_v1_0_init(struct amdgpu_device *adev)

{

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];

	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];



	hub->ctx0_ptb_addr_lo32 =

		SOC15_REG_OFFSET(GC, 0,