Commit a3a88587 authored by George Shen's avatar George Shen Committed by Alex Deucher
Browse files

drm/amd/display: Fix divide-by-zero in DPPCLK and DISPCLK calculation 



[Why]
Certain use cases will pass in zero in the new_clocks parameter for all
clocks. This results in a divide-by-zero error when attempting to round
up the new clock.

When new_clocks are zero, no rounding is required, so we can skip it.

[How]
Guard the division calculation with a check to make sure clocks are not
zero.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarGeorge Shen <george.shen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 04e6931a

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+10 −8
Original line number Diff line number Diff line
@@ -335,15 +335,17 @@ static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, s 
	int dpp_divider = 0;

	int disp_divider = 0;



	if (new_clocks->dppclk_khz) {

		dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR

				* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;

		new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;

	}

	if (new_clocks->dispclk_khz > 0) {

		disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR

				* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;



	// Divide back the previous result to round up to the actual clock value that will be set from divider

	new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;

		new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;

	}

}



static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,

			struct dc_state *context,