Commit a3ba1169 authored by Khiem Nguyen's avatar Khiem Nguyen Committed by Geert Uytterhoeven
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arm64: dts: r8a7795: Add cpuidle support for CA57 cores 



Enable cpuidle (core shutdown) support for R-Car H3 CA57 cores.

Parameters were found after evaluation by gaku.inami.xw@bp.renesas.com; they
help to keep the performance and reduce the power consumption.

Signed-off-by: default avatarKhiem Nguyen <khiem.nguyen.xt@renesas.com>
[dien.pham.ry: Apply new cpuidle parameters]
Signed-off-by: default avatarDien Pham <dien.pham.ry@renesas.com>
Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: default avatarUlrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/1547808474-19427-2-git-send-email-uli+renesas@fpond.eu


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 3c19b46a

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@ a57_0: cpu@0 { 
			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			dynamic-power-coefficient = <854>;

			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;
@@ -169,6 +170,7 @@ a57_1: cpu@1 { 
			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			capacity-dmips-mhz = <1024>;
@@ -182,6 +184,7 @@ a57_2: cpu@2 { 
			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			capacity-dmips-mhz = <1024>;
@@ -195,6 +198,7 @@ a57_3: cpu@3 { 
			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			capacity-dmips-mhz = <1024>;
@@ -264,6 +268,19 @@ L2_CA53: cache-controller-1 { 
			cache-unified;

			cache-level = <2>;

		};



		idle-states {

			entry-method = "psci";



			CPU_SLEEP_0: cpu-sleep-0 {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x0010000>;

				local-timer-stop;

				entry-latency-us = <400>;

				exit-latency-us = <500>;

				min-residency-us = <4000>;

			};

		};

	};



	extal_clk: extal {