Commit a3d63c62 authored by Mohammad Zafar Ziya's avatar Mohammad Zafar Ziya Committed by Alex Deucher
Browse files

drm/amdgpu: Add vcn and jpeg ras support flag 



Add vcn and jpeg ras support options

V2: vcn and jpeg ras flag enabled for aldebaran asic only

V3: vcn and jpeg ras flag disabled for error counter query
Generic poison query interface added
VCN and JPEG ras enabled based on IP version check

V4: vcn and jpeg ras flag moved under ecc flag for dGPU

Signed-off-by: default avatarMohammad Zafar Ziya <Mohammadzafar.ziya@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 425d7a87

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+9 −0
Original line number Diff line number Diff line
@@ -66,6 +66,8 @@ const char *ras_block_string[] = { 
	"mp1",

	"fuse",

	"mca",

	"vcn",

	"jpeg",

};



const char *ras_mca_block_string[] = {
@@ -2205,6 +2207,13 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) 
			dev_info(adev->dev, "SRAM ECC is active.\n");

			adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |

						    1 << AMDGPU_RAS_BLOCK__DF);



			if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0))

				adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |

						1 << AMDGPU_RAS_BLOCK__JPEG);

			else

				adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |

						1 << AMDGPU_RAS_BLOCK__JPEG);

		} else {

			dev_info(adev->dev, "SRAM ECC is not presented.\n");

		}

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

+2 −0
Original line number Diff line number Diff line
@@ -49,6 +49,8 @@ enum amdgpu_ras_block { 
	AMDGPU_RAS_BLOCK__MP1,

	AMDGPU_RAS_BLOCK__FUSE,

	AMDGPU_RAS_BLOCK__MCA,

	AMDGPU_RAS_BLOCK__VCN,

	AMDGPU_RAS_BLOCK__JPEG,



	AMDGPU_RAS_BLOCK__LAST

};