Commit a3e38a55 authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

iio: frequency: admv1014: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: f4eb9ac7 ("iio: frequency: admv1014: add support for ADMV1014")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Antoniu Miclaus <antoniu.miclaus@analog.com>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-70-jic23@kernel.org
parent b3f3f8d2

drivers/iio/frequency/admv1014.c

+1 −1
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ struct admv1014_state { 
	unsigned int			quad_se_mode;

	unsigned int			p1db_comp;

	bool				det_en;

	u8				data[3] ____cacheline_aligned;

	u8				data[3] __aligned(IIO_DMA_MINALIGN);

};



static const int mixer_vgate_table[] = {106, 107, 108, 110, 111, 112, 113, 114,