Commit a4b17f75 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/fbc: Finish polishing FBC1 registers 



Switch all the FBC1 registers over to REG_BTT()/etc.
And while at it add a few more registers/bits that
escaped the net previously.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211104144520.22605-14-ville.syrjala@linux.intel.com


Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
parent 73ab6ec9

drivers/gpu/drm/i915/display/intel_fbc.c

+1 −1
Original line number Diff line number Diff line
@@ -189,7 +189,7 @@ static u32 i965_fbc_ctl2(struct drm_i915_private *i915) 
		FBC_CTL_PLANE(params->crtc.i9xx_plane);



	if (params->fence_id >= 0)

		fbc_ctl2 |= FBC_CTL_CPU_FENCE;

		fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;



	return fbc_ctl2;

}

drivers/gpu/drm/i915/i915_reg.h

+36 −26
Original line number Diff line number Diff line
@@ -3313,28 +3313,38 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   FBC_CTL_INTERVAL(x)		REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))

#define   FBC_CTL_STOP_ON_MOD		REG_BIT(15)

#define   FBC_CTL_UNCOMPRESSIBLE	REG_BIT(14) /* i915+ */

#define   FBC_CTL_C3_IDLE	REG_BIT(13) /* i945gm */

#define   FBC_CTL_C3_IDLE		REG_BIT(13) /* i945gm only */

#define   FBC_CTL_STRIDE_MASK		REG_GENMASK(12, 5)

#define   FBC_CTL_STRIDE(x)		REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))

#define   FBC_CTL_FENCENO_MASK		REG_GENMASK(3, 0)

#define   FBC_CTL_FENCENO(x)		REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))

#define FBC_COMMAND		_MMIO(0x320c)

#define   FBC_CMD_COMPRESS	(1 << 0)

#define   FBC_CMD_COMPRESS		REG_BIT(0)

#define FBC_STATUS		_MMIO(0x3210)

#define   FBC_STAT_COMPRESSING	(1 << 31)

#define   FBC_STAT_COMPRESSED	(1 << 30)

#define   FBC_STAT_MODIFIED	(1 << 29)

#define   FBC_STAT_CURRENT_LINE_SHIFT	(0)

#define FBC_CONTROL2		_MMIO(0x3214)

#define   FBC_CTL_FENCE_DBL	(0 << 4)

#define   FBC_CTL_IDLE_IMM	(0 << 2)

#define   FBC_CTL_IDLE_FULL	(1 << 2)

#define   FBC_CTL_IDLE_LINE	(2 << 2)

#define   FBC_CTL_IDLE_DEBUG	(3 << 2)

#define   FBC_CTL_CPU_FENCE	(1 << 1)

#define   FBC_CTL_PLANE(plane)	((plane) << 0)

#define FBC_FENCE_OFF		_MMIO(0x3218) /* BSpec typo has 321Bh */

#define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4)

#define   FBC_STAT_COMPRESSING		REG_BIT(31)

#define   FBC_STAT_COMPRESSED		REG_BIT(30)

#define   FBC_STAT_MODIFIED		REG_BIT(29)

#define   FBC_STAT_CURRENT_LINE_MASK	REG_GENMASK(10, 0)

#define FBC_CONTROL2		_MMIO(0x3214) /* i965gm only */

#define   FBC_CTL_FENCE_DBL		REG_BIT(4)

#define   FBC_CTL_IDLE_MASK		REG_GENMASK(3, 2)

#define   FBC_CTL_IDLE_IMM		REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)

#define   FBC_CTL_IDLE_FULL		REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)

#define   FBC_CTL_IDLE_LINE		REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)

#define   FBC_CTL_IDLE_DEBUG		REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)

#define   FBC_CTL_CPU_FENCE_EN		REG_BIT(1)

#define   FBC_CTL_PLANE_MASK		REG_GENMASK(1, 0)

#define   FBC_CTL_PLANE(i9xx_plane)	REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))

#define FBC_FENCE_OFF		_MMIO(0x3218)  /* i965gm only, BSpec typo has 321Bh */

#define FBC_MOD_NUM		_MMIO(0x3220)  /* i965gm only */

#define   FBC_MOD_NUM_MASK		REG_GENMASK(31, 1)

#define   FBC_MOD_NUM_VALID		REG_BIT(0)

#define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4) /* 49 reisters */

#define   FBC_TAG_MASK			REG_GENMASK(1, 0) /* 16 tags per register */

#define   FBC_TAG_MODIFIED		REG_FIELD_PREP(FBC_TAG_MASK, 0)

#define   FBC_TAG_UNCOMPRESSED		REG_FIELD_PREP(FBC_TAG_MASK, 1)

#define   FBC_TAG_UNCOMPRESSIBLE	REG_FIELD_PREP(FBC_TAG_MASK, 2)

#define   FBC_TAG_COMPRESSED		REG_FIELD_PREP(FBC_TAG_MASK, 3)









#define FBC_LL_SIZE		(1536)