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Commit a4f8a6e6 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
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clk: renesas: r8a779g0: Add watchdog clock



Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4H (R8A779G0) SoC.

Extracted from a larger patch in the BSP by Kazuya Mizuguchi.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a012e4449b976efbeaabebb983fa6cfc1b9329d3.1662714852.git.geert+renesas@glider.be
parent e312ae92
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