Commit a512807c authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'mlx5-fixes-2022-12-28' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux 

mlx5-fixes-2022-12-28
parents d530ece7 4d1c1379

drivers/net/ethernet/mellanox/mlx5/core/devlink.c

+2 −2
Original line number Diff line number Diff line
@@ -468,7 +468,7 @@ static int mlx5_devlink_enable_roce_validate(struct devlink *devlink, u32 id, 
	bool new_state = val.vbool;



	if (new_state && !MLX5_CAP_GEN(dev, roce) &&

	    !MLX5_CAP_GEN(dev, roce_rw_supported)) {

	    !(MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))) {

		NL_SET_ERR_MSG_MOD(extack, "Device doesn't support RoCE");

		return -EOPNOTSUPP;

	}
@@ -563,7 +563,7 @@ static int mlx5_devlink_eq_depth_validate(struct devlink *devlink, u32 id, 
					  union devlink_param_value val,

					  struct netlink_ext_ack *extack)

{

	return (val.vu16 >= 64 && val.vu16 <= 4096) ? 0 : -EINVAL;

	return (val.vu32 >= 64 && val.vu32 <= 4096) ? 0 : -EINVAL;

}



static const struct devlink_param mlx5_devlink_params[] = {

drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c

+5 −1
Original line number Diff line number Diff line
@@ -459,7 +459,11 @@ static int mlx5e_rx_reporter_diagnose(struct devlink_health_reporter *reporter, 
		goto unlock;



	for (i = 0; i < priv->channels.num; i++) {

		struct mlx5e_rq *rq = &priv->channels.c[i]->rq;

		struct mlx5e_channel *c = priv->channels.c[i];

		struct mlx5e_rq *rq;



		rq = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state) ?

			&c->xskrq : &c->rq;



		err = mlx5e_rx_reporter_build_diagnose_output(rq, fmsg);

		if (err)

drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c

+1 −6
Original line number Diff line number Diff line
@@ -2103,14 +2103,9 @@ mlx5_tc_ct_init_check_support(struct mlx5e_priv *priv, 
static void

mlx5_ct_tc_create_dbgfs(struct mlx5_tc_ct_priv *ct_priv)

{

	bool is_fdb = ct_priv->ns_type == MLX5_FLOW_NAMESPACE_FDB;

	struct mlx5_tc_ct_debugfs *ct_dbgfs = &ct_priv->debugfs;

	char dirname[16] = {};



	if (sscanf(dirname, "ct_%s", is_fdb ? "fdb" : "nic") < 0)

		return;



	ct_dbgfs->root = debugfs_create_dir(dirname, mlx5_debugfs_get_dev_root(ct_priv->dev));

	ct_dbgfs->root = debugfs_create_dir("ct", mlx5_debugfs_get_dev_root(ct_priv->dev));

	debugfs_create_atomic_t("offloaded", 0400, ct_dbgfs->root,

				&ct_dbgfs->stats.offloaded);

	debugfs_create_atomic_t("rx_dropped", 0400, ct_dbgfs->root,

drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c

+8 −1
Original line number Diff line number Diff line
@@ -222,7 +222,7 @@ void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv, 
	int err;



	list_for_each_entry(flow, flow_list, tmp_list) {

		if (!mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, SLOW))

		if (!mlx5e_is_offloaded_flow(flow))

			continue;



		attr = mlx5e_tc_get_encap_attr(flow);
@@ -231,6 +231,13 @@ void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv, 
		esw_attr->dests[flow->tmp_entry_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;

		esw_attr->dests[flow->tmp_entry_index].pkt_reformat = NULL;



		/* Clear pkt_reformat before checking slow path flag. Because

		 * in next iteration, the same flow is already set slow path

		 * flag, but still need to clear the pkt_reformat.

		 */

		if (flow_flag_test(flow, SLOW))

			continue;



		/* update from encap rule to slow path rule */

		spec = &flow->attr->parse_attr->spec;

		rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);

drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c

+5 −0
Original line number Diff line number Diff line
@@ -273,6 +273,11 @@ static int mlx5e_tc_tun_parse_geneve_options(struct mlx5e_priv *priv, 
		 geneve_tlv_option_0_data, be32_to_cpu(opt_data_key));

	MLX5_SET(fte_match_set_misc3, misc_3_c,

		 geneve_tlv_option_0_data, be32_to_cpu(opt_data_mask));

	if (MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,

				       ft_field_support.geneve_tlv_option_0_exist)) {

		MLX5_SET_TO_ONES(fte_match_set_misc, misc_c, geneve_tlv_option_0_exist);

		MLX5_SET_TO_ONES(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist);

	}



	spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;