Commit a53b554b authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
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drm/amd/display: Only flush delta from last command execution



[Why]
We're currently flushing commands that had been previously been
flushed or are currently being processed by the DMCUB when we don't
immediately wait for idle after command execution.

[How]
Avoiding reflushing the data by keeping track of the last wptr.

We'll treat this as the actual rptr by creating a copy of the inbox
and modifying the copy's rptr.

Reviewed-by: default avatarEric Yang <Eric.Yang2@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c09bb36d
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+1 −0
Original line number Diff line number Diff line
@@ -411,6 +411,7 @@ struct dmub_srv {
	struct dmub_srv_base_funcs funcs;
	struct dmub_srv_hw_funcs hw_funcs;
	struct dmub_rb inbox1_rb;
	uint32_t inbox1_last_wptr;
	/**
	 * outbox1_rb is accessed without locks (dal & dc)
	 * and to be used only in dmub_srv_stat_get_notification()
+8 −1
Original line number Diff line number Diff line
@@ -609,6 +609,8 @@ enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,

enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
{
	struct dmub_rb flush_rb;

	if (!dmub->hw_init)
		return DMUB_STATUS_INVALID;

@@ -617,9 +619,14 @@ enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
	 * been flushed to framebuffer memory. Otherwise DMCUB might
	 * read back stale, fully invalid or partially invalid data.
	 */
	dmub_rb_flush_pending(&dmub->inbox1_rb);
	flush_rb = dmub->inbox1_rb;
	flush_rb.rptr = dmub->inbox1_last_wptr;
	dmub_rb_flush_pending(&flush_rb);

		dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);

	dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;

	return DMUB_STATUS_OK;
}