Commit a61794bd authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
Browse files

drm/amdgpu: remove grbm cam index/data operations for gfx v10 



PSP firmware will be responsible for applying the GRBM CAM remapping in
the production. And the GRBM_CAM_INDEX / GRBM_CAM_DATA registers will be
protected by PSP under security policy. So remove it according to the
new security policy.

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ac82902d

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+0 −22
Original line number Diff line number Diff line
@@ -270,25 +270,6 @@ MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 
MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");

MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");



static const struct soc15_reg_golden golden_settings_gc_10_0[] =

{

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),

	/* TA_GRAD_ADJ_UCONFIG -> TA_GRAD_ADJ */

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382),

	/* VGT_TF_RING_SIZE_UMD -> VGT_TF_RING_SIZE */

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2262c24e),

	/* VGT_HS_OFFCHIP_PARAM_UMD -> VGT_HS_OFFCHIP_PARAM */

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x226cc24f),

	/* VGT_TF_MEMORY_BASE_UMD -> VGT_TF_MEMORY_BASE */

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x226ec250),

	/* VGT_TF_MEMORY_BASE_HI_UMD -> VGT_TF_MEMORY_BASE_HI */

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2278c261),

	/* VGT_ESGS_RING_SIZE_UMD -> VGT_ESGS_RING_SIZE */

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2232c240),

	/* VGT_GSVS_RING_SIZE_UMD -> VGT_GSVS_RING_SIZE */

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2233c241),

};



static const struct soc15_reg_golden golden_settings_gc_10_1[] =

{

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -3809,9 +3790,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 
						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));

		break;

	case IP_VERSION(10, 1, 3):

		soc15_program_register_sequence(adev,

						golden_settings_gc_10_0,

						(const u32)ARRAY_SIZE(golden_settings_gc_10_0));

		soc15_program_register_sequence(adev,

						golden_settings_gc_10_0_cyan_skillfish,

						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));