Commit a8121eeb authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-apq8084: move PLL clocks up 



Move PLL clock declarations up, before clock parent tables, so that we
can use pll hw clock fields in the next commit.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-6-dmitry.baryshkov@linaro.org
parent 21c34876

drivers/clk/qcom/gcc-apq8084.c

+81 −81
Original line number Diff line number Diff line
@@ -36,6 +36,87 @@ enum { 
	P_SLEEP_CLK,

};



static struct clk_pll gpll0 = {

	.l_reg = 0x0004,

	.m_reg = 0x0008,

	.n_reg = 0x000c,

	.config_reg = 0x0014,

	.mode_reg = 0x0000,

	.status_reg = 0x001c,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll0",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap gpll0_vote = {

	.enable_reg = 0x1480,

	.enable_mask = BIT(0),

	.hw.init = &(struct clk_init_data){

		.name = "gpll0_vote",

		.parent_names = (const char *[]){ "gpll0" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static struct clk_pll gpll1 = {

	.l_reg = 0x0044,

	.m_reg = 0x0048,

	.n_reg = 0x004c,

	.config_reg = 0x0054,

	.mode_reg = 0x0040,

	.status_reg = 0x005c,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll1",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap gpll1_vote = {

	.enable_reg = 0x1480,

	.enable_mask = BIT(1),

	.hw.init = &(struct clk_init_data){

		.name = "gpll1_vote",

		.parent_names = (const char *[]){ "gpll1" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static struct clk_pll gpll4 = {

	.l_reg = 0x1dc4,

	.m_reg = 0x1dc8,

	.n_reg = 0x1dcc,

	.config_reg = 0x1dd4,

	.mode_reg = 0x1dc0,

	.status_reg = 0x1ddc,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll4",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap gpll4_vote = {

	.enable_reg = 0x1480,

	.enable_mask = BIT(4),

	.hw.init = &(struct clk_init_data){

		.name = "gpll4_vote",

		.parent_names = (const char *[]){ "gpll4" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static const struct parent_map gcc_xo_gpll0_map[] = {

	{ P_XO, 0 },

	{ P_GPLL0, 1 }
@@ -98,33 +179,6 @@ static const char * const gcc_xo_pcie_sleep[] = { 
	"sleep_clk_src",

};



static struct clk_pll gpll0 = {

	.l_reg = 0x0004,

	.m_reg = 0x0008,

	.n_reg = 0x000c,

	.config_reg = 0x0014,

	.mode_reg = 0x0000,

	.status_reg = 0x001c,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll0",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap gpll0_vote = {

	.enable_reg = 0x1480,

	.enable_mask = BIT(0),

	.hw.init = &(struct clk_init_data){

		.name = "gpll0_vote",

		.parent_names = (const char *[]){ "gpll0" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static struct clk_rcg2 config_noc_clk_src = {

	.cmd_rcgr = 0x0150,

	.hid_width = 5,
@@ -161,60 +215,6 @@ static struct clk_rcg2 system_noc_clk_src = { 
	},

};



static struct clk_pll gpll1 = {

	.l_reg = 0x0044,

	.m_reg = 0x0048,

	.n_reg = 0x004c,

	.config_reg = 0x0054,

	.mode_reg = 0x0040,

	.status_reg = 0x005c,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll1",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap gpll1_vote = {

	.enable_reg = 0x1480,

	.enable_mask = BIT(1),

	.hw.init = &(struct clk_init_data){

		.name = "gpll1_vote",

		.parent_names = (const char *[]){ "gpll1" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static struct clk_pll gpll4 = {

	.l_reg = 0x1dc4,

	.m_reg = 0x1dc8,

	.n_reg = 0x1dcc,

	.config_reg = 0x1dd4,

	.mode_reg = 0x1dc0,

	.status_reg = 0x1ddc,

	.status_bit = 17,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll4",

		.parent_names = (const char *[]){ "xo" },

		.num_parents = 1,

		.ops = &clk_pll_ops,

	},

};



static struct clk_regmap gpll4_vote = {

	.enable_reg = 0x1480,

	.enable_mask = BIT(4),

	.hw.init = &(struct clk_init_data){

		.name = "gpll4_vote",

		.parent_names = (const char *[]){ "gpll4" },

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,

	},

};



static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {

	F(100000000, P_GPLL0, 6, 0, 0),

	F(200000000, P_GPLL0, 3, 0, 0),