Commit aa78032c authored by Thierry Reding's avatar Thierry Reding
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arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186 



The standard mmio-sram bindings require the #address- and #size-cells
properties to be 1.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent a10b9a20

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -1216,20 +1216,20 @@ gpu@17000000 { 
	sysram@30000000 {

		compatible = "nvidia,tegra186-sysram", "mmio-sram";

		reg = <0x0 0x30000000 0x0 0x50000>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x30000000 0x50000>;



		cpu_bpmp_tx: shmem@4e000 {

			compatible = "nvidia,tegra186-bpmp-shmem";

			reg = <0x0 0x4e000 0x0 0x1000>;

			reg = <0x4e000 0x1000>;

			label = "cpu-bpmp-tx";

			pool;

		};



		cpu_bpmp_rx: shmem@4f000 {

			compatible = "nvidia,tegra186-bpmp-shmem";

			reg = <0x0 0x4f000 0x0 0x1000>;

			reg = <0x4f000 0x1000>;

			label = "cpu-bpmp-rx";

			pool;

		};