Commit aa79d380 authored by Victor Skvortsov's avatar Victor Skvortsov Committed by Alex Deucher
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drm/amdgpu: Fix wait for RLCG command completion 



if (!(tmp & flag)) condition will always evaluate to true
when the flag is 0x0 (AMDGPU_RLCG_GC_WRITE). Instead check
that address bits are cleared to determine whether
the command is complete.

Signed-off-by: default avatarVictor Skvortsov <victor.skvortsov@amd.com>
Tested-by: default avatarBokun Zhang <bokun.zhang@amd.com>
Reviewed by: Shaoyun.liu <Shaoyun.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fa39f936

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

+1 −1
Original line number Diff line number Diff line
@@ -902,7 +902,7 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v 


		for (i = 0; i < timeout; i++) {

			tmp = readl(scratch_reg1);

			if (!(tmp & flag))

			if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK))

				break;

			udelay(10);

		}

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

+2 −0
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ 
#define AMDGPU_RLCG_WRONG_OPERATION_TYPE	0x2000000

#define AMDGPU_RLCG_REG_NOT_IN_RANGE		0x1000000



#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK	0xFFFFF



/* all asic after AI use this offset */

#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5

/* tonga/fiji use this offset */