Commit ab91f72e authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Stephen Boyd
Browse files

clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks 



The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the
SoC. Update the definition of these clocks to allow this to be wired up
to the appropriate clock source.

Retain "xo" as the global named parent to make the change a nop in the
event that DT doesn't carry the necessary clocks definition.

Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20200106080546.3192125-2-bjorn.andersson@linaro.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent bcd63d22

Documentation/devicetree/bindings/clock/qcom,gcc.yaml

+10 −0
Original line number Diff line number Diff line
@@ -47,6 +47,11 @@ properties: 
        - description: Board XO source

        - description: Board active XO source

        - description: Sleep clock source

      #qcom,gcc-msm8996

      - items:

        - description: XO source

        - description: Second XO source

        - description: Sleep clock source

      #qcom,gcc-msm8998

      - items:

        - description: Board XO source
@@ -65,6 +70,11 @@ properties: 
        - const: bi_tcxo

        - const: bi_tcxo_ao

        - const: sleep_clk

      #qcom,gcc-msm8996

      - items:

        - const: cxo

        - const: cxo2

        - const: sleep_clk

      #qcom,gcc-msm8998

      - items:

        - const: xo

drivers/clk/qcom/gcc-msm8996.c

+28 −7
Original line number Diff line number Diff line
@@ -3046,7 +3046,10 @@ static struct clk_branch gcc_usb3_clkref_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_usb3_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "cxo2",

				.name = "xo",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},
@@ -3060,7 +3063,10 @@ static struct clk_branch gcc_hdmi_clkref_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_hdmi_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "cxo2",

				.name = "xo",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},
@@ -3074,7 +3080,10 @@ static struct clk_branch gcc_edp_clkref_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_edp_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "cxo2",

				.name = "xo",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},
@@ -3088,7 +3097,10 @@ static struct clk_branch gcc_ufs_clkref_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "cxo2",

				.name = "xo",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},
@@ -3102,7 +3114,10 @@ static struct clk_branch gcc_pcie_clkref_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "cxo2",

				.name = "xo",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},
@@ -3116,7 +3131,10 @@ static struct clk_branch gcc_rx2_usb2_clkref_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_rx2_usb2_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "cxo2",

				.name = "xo",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},
@@ -3130,7 +3148,10 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_rx1_usb2_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "cxo2",

				.name = "xo",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},