Commit ac18b610 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Enable FPO for configs that could reduce vlevel 



[Description]
- On high refresh rate DRR displays that support VBLANK naturally,
  UCLK could be idling at DPM1 instead of DPM0 since it doesn't use
  FPO
- To achieve DPM0, enable FPO on these configs even though it can
  support P-State without FPO
- Default disable for now, have debug option to enable

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d29fb7ba

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -873,6 +873,7 @@ struct dc_debug_options { 
	bool dig_fifo_off_in_blank;

	bool temp_mst_deallocation_sequence;

	bool override_dispclk_programming;

	bool disable_fpo_optimizations;

};



struct gpu_info_soc_bounding_box_v1_0;

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -725,6 +725,7 @@ static const struct dc_debug_options debug_defaults_drv = { 
	.min_prefetch_in_strobe_ns = 60000, // 60us

	.disable_unbounded_requesting = false,

	.override_dispclk_programming = true,

	.disable_fpo_optimizations = true,

};



static const struct dc_debug_options debug_defaults_diags = {

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -723,6 +723,7 @@ static const struct dc_debug_options debug_defaults_drv = { 
	.min_prefetch_in_strobe_ns = 60000, // 60us

	.disable_unbounded_requesting = false,

	.override_dispclk_programming = true,

	.disable_fpo_optimizations = true,

};



static const struct dc_debug_options debug_defaults_diags = {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+17 −6
Original line number Diff line number Diff line
@@ -1961,7 +1961,8 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 


	context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;



	if (!pstate_en) {

	if (!pstate_en || (!dc->debug.disable_fpo_optimizations &&

			pstate_en && vlevel != 0)) {

		/* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */

		context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =

			dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
@@ -1985,11 +1986,21 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 
				context->bw_ctx.dml.soc.fclk_change_latency_us =

						dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

			}

			dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);

			dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false);

			if (vlevel_temp < vlevel) {

				vlevel = vlevel_temp;

				maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;

				dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

			pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] !=

					dm_dram_clock_change_unsupported;

				pstate_en = true;

			} else {

				/* Restore FCLK latency and re-run validation to go back to original validation

				 * output if we find that enabling FPO does not give us any benefit (i.e. lower

				 * voltage level)

				 */

				context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;

				context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

				dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);

			}

		}

	}