Commit add74595 authored by John Sheehan's avatar John Sheehan Committed by Greg Kroah-Hartman
Browse files

Staging: comedi: fix code style errors in s626.c 



A patch for s626.c to fix errors reported by
checkpatch.pl tool, namely,
-code indent should use tabs where possible
-"foo * bar" should be "foo *bar"
-trailing statements should be on next line

Signed-off-by: default avatarJohn Sheehan <john.d.sheehan@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 2fa5e380

drivers/staging/comedi/drivers/s626.c

+39 −28
Original line number Diff line number Diff line
@@ -815,7 +815,8 @@ static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it) 
		/*  Write I2C control: abort any I2C activity. */

		MC_ENABLE(P_MC2, MC2_UPLD_IIC);

		/*  Invoke command  upload */

		while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0) ;

		while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)

		    ;

		/*  and wait for upload to complete. */



		/* Per SAA7146 data sheet, write to STATUS reg twice to
@@ -824,7 +825,8 @@ static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it) 
			WR7146(P_I2CSTAT, I2C_CLKSEL);

			/*  Write I2C control: reset  error flags. */

			MC_ENABLE(P_MC2, MC2_UPLD_IIC);	/*  Invoke command upload */

			while (!MC_TEST(P_MC2, MC2_UPLD_IIC)) ;

			while (!MC_TEST(P_MC2, MC2_UPLD_IIC))

			    ;

			/* and wait for upload to complete. */

		}
@@ -1687,7 +1689,8 @@ static int s626_ai_insn_read(struct comedi_device *dev, 
		/*  shift into FB BUFFER 1 register. */



		/*  Wait for ADC done. */

		while (!(RR7146(P_PSR) & PSR_GPIO2)) ;

		while (!(RR7146(P_PSR) & PSR_GPIO2))

		    ;



		/*  Fetch ADC data. */

		if (n != 0)
@@ -1719,7 +1722,8 @@ static int s626_ai_insn_read(struct comedi_device *dev, 
	/*  Wait for the data to arrive in FB BUFFER 1 register. */



	/*  Wait for ADC done. */

	while (!(RR7146(P_PSR) & PSR_GPIO2)) ;

	while (!(RR7146(P_PSR) & PSR_GPIO2))

	    ;



	/*  Fetch ADC data from audio interface's input shift register. */
@@ -2461,8 +2465,7 @@ static void s626_timer_load(struct comedi_device *dev, struct enc_private *k, 
static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };



/*  TrimDac LogicalChan-to-EepromAdrs mapping table. */

static uint8_t trimadrs[] =

    { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };

static uint8_t trimadrs[] = { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };



static void LoadTrimDACs(struct comedi_device *dev)

{
@@ -2560,10 +2563,12 @@ static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val) 
	/*  upload confirmation. */



	MC_ENABLE(P_MC2, MC2_UPLD_IIC);

	while (!MC_TEST(P_MC2, MC2_UPLD_IIC)) ;

	while (!MC_TEST(P_MC2, MC2_UPLD_IIC))

	    ;



	/*  Wait until I2C bus transfer is finished or an error occurs. */

	while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY) ;

	while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY)

	    ;



	/*  Return non-zero if I2C error occured. */

	return RR7146(P_I2CCTRL) & I2C_ERR;
@@ -2677,7 +2682,8 @@ static void SendDAC(struct comedi_device *dev, uint32_t val) 
	 * Done by polling the DMAC enable flag; this flag is automatically

	 * cleared when the transfer has finished.

	 */

	while ((RR7146(P_MC1) & MC1_A2OUT) != 0) ;

	while ((RR7146(P_MC1) & MC1_A2OUT) != 0)

	    ;



	/* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
@@ -2694,7 +2700,8 @@ static void SendDAC(struct comedi_device *dev, uint32_t val) 
	 * finished transferring the DAC's data DWORD from the output FIFO

	 * to the output buffer register.

	 */

	while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0) ;

	while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0)

	    ;



	/* Set up to trap execution at slot 0 when the TSL sequencer cycles

	 * back to slot 0 after executing the EOS in slot 5.  Also,
@@ -2730,7 +2737,8 @@ static void SendDAC(struct comedi_device *dev, uint32_t val) 
		 * from 0xFF to 0x00, which slot 0 causes to happen by shifting

		 * out/in on SD2 the 0x00 that is always referenced by slot 5.

		 */

		while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) ;

		while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0)

		    ;

	}

	/* Either (1) we were too late setting the slot 0 trap; the TSL

	 * sequencer restarted slot 0 before we could set the EOS trap flag,
@@ -2746,7 +2754,8 @@ static void SendDAC(struct comedi_device *dev, uint32_t val) 
	 * the next DAC write.  This is detected when FB_BUFFER2 MSB changes

	 * from 0x00 to 0xFF.

	 */

	while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0) ;

	while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0)

	    ;

}



static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage)
@@ -2785,10 +2794,12 @@ static void DEBItransfer(struct comedi_device *dev) 


	/*  Wait for completion of upload from shadow RAM to DEBI control */

	/*  register. */

	while (!MC_TEST(P_MC2, MC2_UPLD_DEBI)) ;

	while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))

	    ;



	/*  Wait until DEBI transfer is done. */

	while (RR7146(P_PSR) & PSR_DEBI_S) ;

	while (RR7146(P_PSR) & PSR_DEBI_S)

	    ;

}



/*  Write a value to a gate array register. */